Semiconductor device and method of fabricating the same

Details Semiconductor device and method of fabricating the same Semiconductor device and method of fabricating the same

2005-12-13

2005-12-13

Abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S348000

Reexamination Certificate

active

06975001

ABSTRACT:
A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

REFERENCES:
patent: 4-34980 (1992-02-01), None
patent: 11-135795 (1999-05-01), None
patent: 2000-252471 (2000-09-01), None
patent: 2000-269509 (2000-09-01), None
patent: 2000-332250 (2000-11-01), None
patent: 2001-024202 (2001-01-01), None
patent: WO 03/023865 (2003-03-01), None
Yo-Hwan Koh, et al “Body-Contacted SOI MOSFET Structure with Fully Bulk CMOS Compatible Layout and Process”,IEEE Electron Device Letters, vol. 18, No. 31 (Mar. 3, 1997), pp. 102-104.
W. Chen, et al.Suppression of the SOI Floating-body Effects by Linked-body Device Structure, 1996 Symposium on VLSI Technology Digest of Technical Papers, (1996), pp. 92-93.
S. Maeda, et al.,Impact of 0.18 μm SOI CMOS Technology using Hybrid Trench Isolation with High Resistivity Substrate on Embedded RF/Analog Applications, 2000 Symposium on VLSI Technology Digest of Technical Papers, (2000), pp. 154-155.
English Translation of Japanese Publication No.: 11-135795, Publication Date: May 21, 1999.

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