Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-14
2003-04-15
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S253000, C438S254000, C438S397000, C438S399000, C438S238000, C257S300000
Reexamination Certificate
active
06548845
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a capacitor over bit line structure and a method of fabricating thereof.
Furthermore, the present invention relates to a semiconductor device having a wiring pattern formed between two insulating films and a method of fabricating thereof.
This application is counterparts of Japanese patent applications, Serial Number 281590/1999, filed Oct. 1, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
Conventional semiconductor device and its fabricating method are explained by using an example. A DRAM (Dynamic Random Access Memory) having CMOS (Complementary Metal Oxide Semiconductor) structure is used as the example.
A DRAM that has a capacitor over bit line structure (it is called COB structure hereinafter) is known as a conventional DRAM. This structure intends to improve the degree of integration of DRAM by forming a capacitor at a layer located over a bit line.
FIG. 7
is a cross sectional view showing roughly the DRAM having the COB structure.
In
FIG. 7
, an active region (it is also called as an element formation region)
702
is provided in an n-well
701
formed in a silicon substrate
700
. High concentration impurity regions
703
functioned as a source or a drain of a MOS transistor are formed on a surface of the active region
702
and are formed on a region adjacent to the surface. A region provided between the active regions
703
serves as a channel region
704
.
A word line
706
served as a gate electrode is formed on a gate oxide film
705
which is formed over the channel region
704
. A side wall spacers
707
are formed on side walls of the word lines
706
. Surfaces of the gate oxide film
705
, the word lines
706
and the side wall spacers
707
are covered with Non Silicate Glass (it is called hereinafter NSG) film
708
.
A first Boro-Phospho Silicate Glass (it is called hereinafter BPSG) film
709
is formed on the entire surface of the NSG film
708
. A bit line
710
is formed on the first BPSG film
709
. The bit line
710
is composed of a polycrystalline silicon layer
710
a
and a tungsten silicide (WSix) layer
710
b
. The shape of the bit line
710
as illustrated in
FIG. 7
is obtained by using a conventional photo-lithography technology. The bit line
710
is connected to the high concentration impurity region
703
by way of a polycrystalline silicon
712
formed in a contact hole
711
.
A second BPSG film
713
is formed over an entire surface of the first BPSG film
709
. A capacitor
714
is formed on the second BPSG film
713
. The capacitor
714
is composed of an electrode layer
714
a
made of polycrystalline silicon, an insulating thin film
714
b
made of silicon nitride film and an electrode layer
714
c
made of polycrystalline silicon. The electrode layer
714
a
is formed on the second BPSG film
713
. The insulating thin film
714
b
is deposited over the electrode layer
714
a
so as to cover a surface of the electrode layer
714
a
and a surface of the second BPSG film
713
. The electrode layer
714
c
is deposited on the insulating thin film
714
b
after performing a healing oxidation process to remove defect of the insulating thin film
714
b
. The capacitor
714
is connected to the high concentration impurity region
703
by way of the polycrystalline silicon
715
formed in a contact hole
712
. In addition, a protection film or the like is formed on a surface of the electrode layer
714
c
. (not illustrated in
FIG. 7
)
By adopting such structure (namely, COB structure), it is possible to enlarge area of the capacitor
714
without reducing the degree of integration of DRAM. Therefore, such structure is effective when increasing capacity of the capacitor
714
.
In the case that a structure that has the capacitor
714
provided on the first BPSG film
709
and the bit line
710
provided on the second BPSG film
713
, a diameter of the contact hole
711
must be set small in order to enlarge the area of the capacitor
714
. However, minimizing the diameter has limitations. Therefore, the structure prevents the improvement of the degree of the integration.
On the other hand, in the COB structure as illustrated in
FIG. 7
, the contact hole
711
does not serve as an obstacle when increasing the area of the capacitor
714
. Thus, in the COB structure, it is possible to enlarge the area of the capacitor
714
without reducing the degree of the integration.
However, it is difficult to obtain the capacitor
714
having a large capacitance by increasing the area of the capacitor
714
. For this reason, in order to obtain the capacitor
714
having the larger capacitance, reducing thickness of the insulating thin film
714
b
is needed.
However, if the thickness of the insulating thin film
714
b
is made thin, the bit line
710
becomes being easy to oxidize in a fabrication process of DRAM. The reason is explained as follows.
As mentioned above, the healing oxidation process is carried out to remove the defect of the silicon nitride film in the fabrication process of DRAM. When the silicon nitride film is very thick, the silicon nitride film serves as a mask. Thus, an oxidation nucleus, which occurs at the healing oxidation process, does not reach to the bit line
710
easily. In this case, the bit line
710
is prevented from being oxidized.
On the other hand, when the silicon nitride film is very thin, the silicon nitride does not serve as the mask well. Thus, the oxidation nucleus reaches to the bit line
710
easily. As a result, the bit line
710
is oxidized easily.
In the conventional DRAM, as enhancing the high integration, the bit line
710
becomes being easy to oxidize. The oxidation of the bit line
710
causes a decrease of yield and reliability of DRAM.
Such this problem is not restricted to DRAM. This problem occurs at a semiconductor device which has a wiring pattern provided between two insulating layers.
Consequently, there has been a need for an improved semiconductor device that may prevent such wiring pattern from being oxidized.
SUMMARY OF THE INVENTION
It is an object of the present invention is to provide a semiconductor device that may prevent a wiring, which is provided between two insulating layers, from being oxidized.
It is another object of the present invention is to provide a semiconductor device that may prevent a bit line shift.
According to one aspect of the present invention, for achieving one or more of the above objects, there is provided a semiconductor device which includes a semiconductor substrate, a gate electrode formed over the semiconductor substrate and a first interlevel insulating layer which is formed over the semiconductor substrate and has first and second contact holes defined by the first interlevel insulating layer. The semiconductor device also includes a first wiring pattern formed in the first contact hole and on the first interlevel insulating layer, a protection layer covering the first wiring pattern and a second interlevel insulating layer which is formed over the first interlevel insulating layer and has a third contact hole defined by the second interlevel insulating layer. The semiconductor device further includes the third contact hole being located on the second contact hole and a second wiring pattern formed in the second and third contact holes and on the second interlevel insulating layer.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.
REFERENCES:
patent: 6150689 (2000-11-01), Narui et al.
patent: 6159786 (2000-12-01), Chiang et al.
patent: 6268244 (2001-07-01), Park
Anya Igwe U.
Oki Electric Industry Co. Ltd.
Smith Matthew
Volentine & Francos, PLLC
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