Semiconductor device and method of fabricating the same

Details Semiconductor device and method of fabricating the same Semiconductor device and method of fabricating the same

2000-12-01

2002-12-24

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S520000, C438S302000, C438S305000

Reexamination Certificate

active

06498085

ABSTRACT:

This Application claims the benefit of Korean application No. 3939/2000 filed on Jan. 27, 2000 which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The claimed invention relates to a semiconductor device and a method of fabricating the semiconductor device. More particularly, the claimed invention relates to a method of fabricating the semiconductor device wherein a hump on a subthreshold current slope is eliminated.
2. Discussion of the Related Art
A conventional n-channel metal oxide semiconductor field effect transistor (MOSFET) device is schematically illustrated in
FIG. 1. A
semiconductor substrate
10
is divided into an active region
11
and an isolation region
12
. The substrate
10
is a p-type substrate doped with p-type impurities, such as Boron (B). The active region
11
forms a transistor, and the isolation region
12
electrically isolates the transistor from other transistors (not shown). It is known to form the isolation region
12
using a field oxide film which is formed by a local oxidation of silicon (LOCOS) method. It is also known to use a shallow trench isolation (STI) method to enhance the integrity of the semiconductor.
A gate electrode
13
is formed across a center of the active region
11
. A source
14
and a drain
15
are formed in the active region
11
. The source
14
and the drain
15
are separated by and are on opposing sides of the gate electrode
13
. The source
14
and the drain
15
are doped with n-type impurities, such as phosphorus (P) or arsenic (As).
A disadvantage of using the trench isolation structure described above to fabricate n-channel transistors is that a hump occurs in a subthreshold current region. Electric fields concentrate along ends of a channel region (not shown), so that the threshold voltage is lower along the ends of the channel region than at a center portion (not shown) of the channel. The result is current leakage due to subthreshold current flows at the ends of the channel.
The areas where subthreshold current leakage occurs are indicated by A
1
and A
2
in
FIG. 1. A
first area A
1
is elliptically shaped with a first major axis parallel to a longitudinal axis of the substrate
10
. A first minor axis of the first area A
1
lies on an axial axis of the substrate
10
. A first region of the first area A
1
spans the first major axis and encompasses a first portion of the gate electrode
13
and two equal portions of the isolation region
12
, the two equal portions of the isolation region
12
being opposite the gate electrode
13
. A second region of the first area A
1
spans the first major axis and encompasses a second portion of the gate electrode
13
, a first portion of the source
14
and a first portion of the drain
15
, the first source portion being equal in surface area to the first drain portion.
A second area A
2
is elliptically shaped with a second major axis parallel to the longitudinal axis of the substrate
10
. A second minor axis of the second area A
2
lies on the axial axis of the substrate
10
. A first region of the second area A
2
spans the second major axis and encompasses a third portion of the gate electrode
13
, a second portion of the source
14
and a second portion of the drain
15
, the second source portion being equal in surface area to the second drain portion. A second region of the second area A
2
spans the second major axis and encompasses a fourth portion of the gate electrode
13
and two equal portions of the isolation region
12
being opposite the gate electrode
13
.
Subthreshold current leakage occurs in the first area A
1
and the second area A
2
. To solve this problem, it is known to increase the concentration of impurities, such as B at the ends of the channel region (not shown). In other words, a conventional solution to the hump occurrence is to increase the threshold voltage at the ends of the channel by implanting B ions into the sidewalls of the channel. However, this conventional solution results in decreased performance of the semiconductor device.
SUMMARY OF THE INVENTION
The claimed invention relates to a semiconductor device and a method of fabricating the semiconductor device that substantially obviates the decreased performance of semiconductor devices due to the limitations and disadvantages of the related art described above.
Accordingly, it is an object of the claimed invention to provide a gate electrode with differently doped parts so that a threshold voltage along a channel is substantially uniform. Another object of the claimed invention is to maintain the threshold voltage at ends of the channel.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purposes of the claimed invention, as embodied and broadly described, a semiconductor device of the claimed invention and a method of fabricating the device includes a semiconductor substrate divided into an isolation region and an active region. A gate oxide film is formed on a first upper surface of the active region. A gate electrode is formed on a second upper surface of the gate oxide film, the gate electrode having a first part and a second part, wherein the first part is more lightly doped with impurities than the second part. A channel is formed in an upper end of the active region proximate the gate electrode. A source is formed in the active region at a first side of the gate electrode and a drain is formed in the active region at a second side of the gate electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


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patent: 4988638 (1991-01-01), Huang et al.
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patent: 5891782 (1999-04-01), Hsu et al.
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patent: 6091118 (2000-07-01), Duane
patent: 6291325 (2001-09-01), Hsu
patent: 6323985 (2001-11-01), Maloney

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