Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-28
2002-06-04
Trinh, Michael (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000, C257S406000
Reexamination Certificate
active
06399986
ABSTRACT:
This application claims the benefit of Korean Application No. 98-37796 filed on Sep. 14, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving degree of integration and preventing short channel effect in the semiconductor device.
2. Discussion of the Related Art
A recent multimedia system is capable of displaying videos, voices and characters at the same time. Thus, it becomes important to have various, complicated, and improved functions as well as smaller size and lighter weight. To meet such demands, technologies for forming semiconductor circuits on one-chip having various functions have been developed.
A plurality of semiconductor circuits formed on one-chip have various functions and are operated by different power supplies. Each of the circuits should be constructed to be able to perform its own function when they are formed on the same semiconductor substrate. Accordingly, it is required that transistors having various operating voltages should be formed on the same semiconductor substrate. This can be achieved by forming various thicknesses of gate oxides to properly control threshold voltages.
FIG. 1
shows a cross-sectional view of a semiconductor device according to a related background art. As shown in
FIG. 1
, a field oxide layer
19
defining first and second transistor regions T
11
and T
12
in a field area F
11
is formed on a p-type semiconductor substrate
11
. The field oxide layer
19
is formed by a shallow trench isolation (STI) method. For example, a trench
17
having a predetermined depth in the semiconductor substrate
11
is filled with silicon oxide. Alternatively, the field oxide layer
19
may be formed by local oxidation of silicon (LOCOS).
First and second gates
25
and
26
on first and second gate oxide layers
21
and
23
are formed at predetermined portions of the first and second transistor regions T
11
and T
12
, respectively. The first gate oxide layer
21
is formed at the first transistor region Tll by two separate thermal oxidations while the second gate oxide layer
23
is formed at the second transistor region T
12
by a single thermal oxidation. Thus, the first gate oxide
21
becomes thicker than the second gate oxide
23
.
First and second diffusion regions
28
and
29
for a source and drain are formed in the first and the second transistor regions T
11
and T
12
of the semiconductor substrate
11
. The first and second diffusion regions
28
and
29
are formed by heavily doping with n-type impurities using the first and the second gates
25
and
26
as ion-implantation masks.
FIGS. 2A
to
2
E are cross-sectional views illustrating the process steps of fabricating a semiconductor device according to the related background art.
Initially referring to
FIG. 2A
, a buffer oxide layer
13
is formed on a semiconductor substrate
11
by thermal oxidation. A hard mask layer
15
is then formed on the buffer oxide layer
13
by depositing silicon nitride thereon by chemical vapor deposition (CVD).
Thereafter, first and second transistor regions T
11
and T
12
are defined by patterning the hard mask layer
15
and the buffer oxide layer
13
through photolithography, so that a portion of the semiconductor substrate
11
is exposed as a field area F
11
.
Referring to
FIG. 2B
, a field oxide layer
19
electrically isolating the first transistor region T
11
from the second transistor region T
12
is formed at the field area F
11
.
In this process, a trench
17
having a predetermined depth is formed at the field area F
11
using the hard mask layer
15
(shown in
FIG. 2A
) on the first and second transistor regions T
11
and T
12
of the semiconductor substrate
11
. The trench
17
is then filled with silicon oxide by depositing silicon oxide including the hard mask layer
15
by CVD. A field oxide layer
19
is formed by chemical-mechanical polishing (CMP) to expose the hard mask layer
15
and to have the silicon oxide remain only in the trench
17
. The field oxide layer
19
may be formed by either LOCOS or STI.
Then, the hard mask layer
15
and the buffer oxide layer
13
(shown in
FIG. 2A
) on the first and second transistor regions T
11
and T
12
are removed from the semiconductor substrate
11
.
In
FIG. 2C
, a first gate oxide layer
21
is formed on the first and second transistor regions T
11
and T
12
of the semiconductor substrate
11
by thermal oxidation. The first gate oxide layer
21
on the second transistor region T
12
is then removed by photolithography. Thus, only the first gate oxide layer
21
at the first transistor region T
11
remains on the semiconductor substrate
11
.
FIG. 2D
shows a second gate oxide layer
23
formed on the exposed surface of the second transistor region T
12
of the semiconductor substrate
11
by thermal oxidation. In this process, the first gate oxide layer
23
at the first transistor region T
11
becomes thicker. As a result, the first gate oxide layer
21
is thicker than the second gate oxide layer
23
.
Referring to
FIG. 2E
, polycrystalline silicon doped with impurities is deposited on the first and second gate oxide layers
21
and
23
and the field oxide layer
19
by CVD. Then, first and second gates
25
and
26
are formed by patterning the polycrystalline silicon. The first and second gate oxide layers
21
and
23
, thus, remain at predetermined portions of the first and second transistor regions T
11
and T
12
of the semiconductor substrate
11
.
First and second diffusion regions
28
and
29
for a source and drain of first and second transistors are formed by heavy ion-implantation with n-type impurities using the first and second gates
25
and
26
as masks.
As explained in the foregoing description, the semiconductor device according to the related background art is fabricated by forming a first gate oxide layer only on a first transistor region of a semiconductor substrate and by forming a second gate oxide layer on the exposed surface of a second transistor region of the semiconductor substrate by thermal oxidation. In this process, the first gate oxide layer on the first transistor region becomes thicker than the second gate oxide layer. Hence, transistors having a plurality of gate oxide layers which have different thicknesses are fabricated by the previously described background art method.
However, the above-mentioned method has the following drawbacks. For example, a desirable thickness of the gate oxide layers cannot be readily achieved because the gate oxide layers should be etched and re-oxidized. Moreover, since the gates are formed on the semiconductor substrate, the planarization of multi-layered wires becomes worse, and a short channel effect occurs due to reduction in size of the device.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor device and a method fabricating method the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a semiconductor device of which degree of integration is improved and in which gate oxide layers are easily controlled in thickness.
Another object in the present invention is to provide a semiconductor device in which planarization in multi-layered wires is improved and in which a short channel effect is prevented.
A further object of the present invention is to provide a method of fabricating a semiconductor device wherein a plurality of gate oxide layers are easily formed and the thickness of the gate oxide layers are easily controlled.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
Trinh Michael
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