Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-16
2003-06-17
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06581188
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of designing a semiconductor device referred to as a system LSI, for example, and a semiconductor device obtained by this method.
2. Description of the Background Art
Refinement of semiconductor devices so progresses that it is said that all LSIs loaded on a mother board of a personal computer, for example, can be integrated into a single chip in the near future.
A device obtained by implementing control of a complicated application system is referred to as a system LSI. This can be regarded as a developed mode of ASIC (application specific IC). A portable telephone is mentionable as a current familiar example loaded with a system LSI. Some time ago the portable telephone was so large-sized and high-priced that only a few people possessed the same. However, the portable telephone has recently come into wide use due to miniaturization and cost reduction resulting from progress in refinement of the semiconductor device.
As hereinabove described, various advantages such as reduction of power consumption and improvement of the signal processing speed can be attained in addition to miniaturization of the system itself and cost reduction by integrating the largest possible number of components forming the system into a single chip.
It is said that not only the system itself but also the culture around the same remarkably changes in the coming age of such a system LSI. Design·manufacturing of the LSI is no exception.
In relation to design·manufacturing of the LSI, a system designer designs a system including a memory Ca
1
and a logic circuit Ca
2
(including a CPU, a control circuit controlling the memory Ca
1
and the CPU etc.) in general, as shown in FIG.
28
. Then, a circuit designer draws a circuit diagram Ca including the memory Ca
1
and the logic circuit Ca
2
with conventional CAD (computer aided design), and converts the circuit diagram to layout data Da
1
. Then, a system LSI is completed on the basis of the layout data Da
1
through a manufacturing process A. Thus, the circuit diagram drawn by the circuit designer on the CAD forms the system as such. In other words, this is substantially equal to such a situation that the circuit designer designs the system, and it is predicted that design·manufacturing from design to completion of the system is extremely simplified as equivalently shown in FIG.
29
.
As hereinabove described, a number of advantages can be attained not only for the LSI itself but for design-manufacturing around the same when integrating the largest possible number of circuits forming the system into a single chip.
However, it may be difficult to integrate all circuits forming a system into a single chip. In consideration of requirements (external factors) such as increase of the access speed to the memory, reduction of power consumption in the system, a bulk memory, the type of the memory etc., for example, the memory Ca
1
may not be manufacturable through the manufacturing process A. In this case, a certain circuit designer draws the memory Ca
1
with the conventional CAD and converts this circuit diagram to layout data Da
2
, for example. Then, a chip loaded with the memory Ca
1
is completed on the basis of the layout data Da
2
through a manufacturing process B. On the other hand, another circuit designer draws the logic circuit Ca
2
with the conventional CAD and converts this circuit diagram to layout data Da
3
. Then, a chip loaded with the logic circuit Ca
2
is completed on the basis of the layout data Da
3
through the manufacturing process A. These two chips are loaded on a board, for finally completing a system satisfying the aforementioned requirements.
If a requirement R
1
(external factor) for a multi-chip system (divided into a plurality of chips) rather than a single-chip system occurs in consideration of the cost in an intermediate stage of design with the CAD, for example, the circuit design must be performed again.
Although various advantages can be attained in a single-chip system as described above, the system must be designed in consideration of whether or not to integrate the circuits into a single chip in response to external factors in practice, disadvantageously leading to a heavy burden imposed on the designer.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor device comprises a logic circuit, a plurality of types of memories, and a memory control circuit interposed between the logic circuit and all of the plurality of types of memories for setting the response time of each of the plurality of types of memories as viewed from the logic circuit.
According to the first aspect, the memory control circuit sets the response time of each of the plurality of memories as viewed from the logic circuit, whereby the logic circuit can control the plurality of memories regardless of the types thereof.
According to a second aspect of the present invention, the memory control circuit includes a delay time set circuit for setting a delay, time for a control signal propagated from the logic circuit to each of the plurality of types of memories.
According to the second aspect, the delay time set circuit sets the delay time for the control signal, whereby the response time can be set.
According to a third aspect of the present invention, the memory control circuit includes a cache memory interposed between the logic circuit and the memories.
According to the third aspect, the response time can be set by providing the cache memory.
The present invention is also directed to a method of designing a semiconductor device. According to a fourth aspect of the present invention, a method of designing a semiconductor device comprises steps of (a) inputting data related to the configuration of a system in CAD (computer aided design) employed for designing the system, and (b) extracting data formable as a single chip from the data by the CAD.
According to the fourth aspect, a designer may not determine which one of system data input in the CAD is to be included in the single chip, whereby the burden imposed on the designer can be reduced.
According to a fifth aspect of the present invention, the system includes a memory and a logic circuit, and the step (b) includes a step (b-1) of extracting a memory impossible to design in a single chip with the logic circuit on the basis of data related to the configuration of the memory.
According to the fifth aspect, the semiconductor device is designed while taking out the memory from the chip on which the logic circuit is designed, whereby the space area of the chip on which the logic circuit is designed is increased to readily satisfy design conditions.
According to a sixth aspect of the present invention, a memory having a higher processing speed than a memory arranged with the logic circuit is extracted in the step (b-1).
According to the sixth aspect, the memory can be equally handled in point of the operating speed as viewed from the logic circuit, whereby the design is simplified.
According to a seventh aspect of the present invention, a memory control circuit for setting the response time of the memory as viewed from the logic circuit is arranged between the logic circuit and the memory.
According to the seventh aspect, the memory can be equally handled in point of the operating speed as viewed from the logic circuit, whereby the design is simplified.
According to an eighth aspect of the present invention, a memory having a power supply voltage different from that for the logic circuit is extracted in the step (b-1).
According to the eighth aspect, the CAD extracts a memory causing inconvenience when supplied with the same power supply voltage as that for the logic circuit, whereby the design is simplified.
According to a ninth aspect of the present invention, the step (a) includes a step (a-1) of displaying an image showing the data, and the step (b-1) includes a step (b-1-1) of making a display for rendering an image corresponding to data satisfying the single-chip
Hosomi Syunsuke
Saito Makiko
Mitsubishi Denki & Kabushiki Kaisha
Niebling John F.
Whitmore Stacy A
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