Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-03-30
2009-06-23
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
07552369
ABSTRACT:
A semiconductor device includes a memory cell array, in which bit lines intersect word lines to form a memory cell. Representative pads are selected from among pads. Data input to the representative pads is decompressed to data corresponding to all of the pads, and is written in corresponding memory cells. The data is read and divided into number of groups corresponding to number of the representative pads. It is determined whether the data in each group coincide with the data input to the representative pads. Output to the representative pads is controlled based on a result of the determination.
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“Matrix-based test vector decompression using an embedded processor” Balakrishnan et al. This paper appears in: Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on Publication Date: 2002 On pp. 159-165 ISSN: 1063-6722 ISBN: 0-7695-1831-1 INSPEC Accession No. 7604200.
JP Office Action dated Jan. 27, 2009, 4 pages.
Arent Fox LLP.
Britt Cynthia
Fujitsu Microelectronics Limited
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