Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-05
2001-05-22
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S383000, C257S384000, C257S751000, C257S773000
Reexamination Certificate
active
06236090
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it relates to an improvement for reducing contact resistance between an electrode and a semiconductor substrate.
2. Description of the Background Art
FIG. 42
is a front sectional view showing the structure of a conventional semiconductor device
151
forming the background of the present invention. The conventional semiconductor device
151
comprises a MOSFET (metal oxide semiconductor field-effect transistor) on a major surface of a silicon semiconductor substrate
51
. Throughout the specification, an insulated gate FET having a non-metal gate electrode is also referred to as a MOSFET, according to the custom in the related field.
A pair of n-type semiconductor layers
57
are selectively formed in the major surface of the semiconductor substrate
51
exposing a p-type semiconductor layer in a region enclosed with a pair of element isolation layers
52
. The surface layer part of the major surface of the semiconductor substrate
51
enclosed with the pair of semiconductor layers
57
corresponds to a channel region CH of the MOSFET. The semiconductor layers
57
correspond to source/drain regions of the MOSFET. An insulator film
53
is formed on the major surface of the semiconductor substrate
51
, and a gate electrode
55
is formed on the insulator film
53
to be opposed to the channel region CH. Side surfaces of the gate electrode
55
are covered with insulating side walls
56
.
An insulator layer
58
is formed to entirely cover the aforementioned structure formed over the semiconductor substrate
51
. In this insulator layer
58
, a pair of contact holes
59
are selectively formed on positions located immediately above the pair of semiconductor layers
57
, while a contact hole
71
is selectively formed on a position located immediately above the gate electrode
55
.
The contact holes
59
are charged with conductive main electrodes
64
through a barrier layer
62
. Consequently, the pair of main electrodes
64
are connected to the pair of semiconductor layers
57
. Similarly, the contact hole
71
is charged with a conductive gate wire
72
through the barrier layer
62
. Consequently, the gate wire
72
is connected to the gate electrode
55
.
As understood from
FIG. 43
showing a part J of
FIG. 42
in an enlarged manner, silicide layers
63
are formed on the interfaces between the barrier layer
62
and the semiconductor layers
57
and that between the barrier layer
62
and the gate electrode
55
respectively. Thus, the semiconductor device
151
has the silicide layers
63
interposed between the main electrodes
64
and the semiconductor layers
57
and between the gate wire
72
and the gate electrode
55
, for suppressing contact resistance therebetween.
The contact resistance between each main electrode
64
and each semiconductor layer
57
is given by the total sum of the resistance of the main electrode
64
, the interface resistance between the main electrode
64
and the barrier layer
62
, the resistance of the barrier layer
62
, the interface resistance between the barrier layer
62
and the silicide layer
63
, the resistance of the silicide layer
63
and the interface resistance between the silicide layer
63
and the semiconductor layer
57
. Among these resistance elements, the interface resistance between the silicide layer
63
and the semiconductor layer
57
is the maximum. Therefore, the interface resistance between the silicide layer
63
and the semiconductor layer
57
dominates the contact resistance between the main electrode
64
and the semiconductor layer
57
.
The interface resistance R between the silicide layer
63
and the semiconductor layer
57
is expressed as follows:
R=&rgr;/SA . . . (1)
where &rgr; represents the interface resistivity between the silicide layer
63
and the semiconductor layer
57
and SA represents the contact area on the interface between the silicide layer
63
and the semiconductor layer
57
.
Following recent refinement of the semiconductor device, the diameter of the contact hole
59
tends to be reduced. Consequently, the contact area SA is reduced, to increase while the interface resistance R. Since the diameter of the contact hole
71
also tends to be reduced, the contact resistance between the gate wire
72
and the gate electrode
55
is also increased similarly to that between the main electrode
64
and the semiconductor layer
57
. However, the increase of the contact resistance between the main electrode
64
feeding a main current and the semiconductor layer
57
is more significant.
In order to reduce the interface resistance R, two countermeasures for reducing the interface resistivity &rgr; and enlarging the contact area SA are assumable from the expression (1). Prior Art noting each of these countermeasures is known in the art.
Each of Japanese Patent Laying-Open Gazettes Nos. 8-191053 (1996) and 9-115860 (1997) discloses a technique employing silicide epitaxially growing toward a silicon substrate. On a general interface between silicide and silicon, a number of defects are present due to mismatching in crystal structure. Consequently, the defects cause scattering when carriers pass through the interface, to increase the interface resistivity &rgr;.
On the other hand, the interface resistivity &rgr; is reduced on the interface between silicide epitaxially growing on a silicon substrate and silicon, due to a small amount of crystal defects. In other words, the prior art disclosed in each of the aforementioned gazettes achieves reduction of the interface resistivity &rgr;. In the prior art, however, the contact area SA cannot be enlarged.
Japanese Patent Laying-Open Gazette No. 3-280532 (1991) discloses a technique of reducing the contact resistance between an electrode and a semiconductor substrate by forming fine irregularities on the bottom portion of a contact hole. According to this technique, the contact area SA can be enlarged without increasing the diameter of the contact hole. However, the interface resistivity &rgr; cannot be reduced.
While either the interface resistivity &rgr; or the contact area SA can be improved in the prior art as described above, no technique of effectively reducing the contact resistance between an electrode and a semiconductor substrate by improving both these elements has been known in the art.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor device comprises a semiconductor substrate having a major surface, an electrode formed on the semiconductor substrate, and a metal semiconductor compound layer interposed between the electrode and the semiconductor substrate and provided with an epitaxial growth layer at least partially inclined against the major surface.
In the semiconductor device according to the first aspect of the present invention, the metal semiconductor compound layer interposed between the electrode and the semiconductor substrate has the epitaxial growth layer at least partially inclined against the major surface of the semiconductor substrate, whereby the area of the interface between the epitaxial growth layer and the semiconductor substrate is enlarged and the interface resistivity is reduced. Therefore, the contact resistance between the electrode and the semiconductor substrate is effectively reduced.
According to a second aspect of the present invention, the semiconductor substrate comprises a semiconductor layer selectively formed in the major surface and containing an impurity, the semiconductor device further comprises an insulator layer formed on the major surface, the insulator layer defines a contact hole selectively opening on the semiconductor layer, the electrode is embedded in the contact hole and connected to the semiconductor layer, a main part of the metal semiconductor compound layer is formed only in a region of the major surface located immediately under the contact h
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tran Minh Loan
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