Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-07
2002-01-29
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S351000, C257S365000, C257S368000, C438S149000, C438S157000, C438S176000, C438S283000
Reexamination Certificate
active
06342717
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having MOSFETs in which semiconductor active layers for forming element active regions have for example silicon-on-insulator (SOI) type substrate separation structures and back side gate electrodes are buried in an insulating layer for substrate separation, and to a method for producing the same. More specifically, the present invention relates to an improvement of the characteristics of a semiconductor device by changing the thickness of the back side gate insulating film.
2. Description of the Related Art
It has been known that complete separation of elements from each other becomes easy by an SOI structure and that suppression of soft-error or latchup peculiar to a complementary metal-oxide-semiconductor (CMOS) transistor becomes possible. Studies have been conducted on increasing the speed and increasing the reliability of CMOS transistor LSIs by an SOI structure having a silicon active layer having a thickness of about 500 nm from a relatively early stage.
Recently it has been learned that by reducing the thickness of the active layer of the SOI structure to about 100 nm and/or controlling also an impurity concentration of the channel to a relatively low state to achieve conditions for substantially the silicon active layer to become fully depleted, further excellent performance such as the suppression of a short channel effect and an improvement of a current drive capability of the MOS transistor can be obtained.
The two leading methods for forming this SOI layer are the separation by implanted oxygen (SIMOX) and using wafer bonding, both of which have become more perfected and have become more well known.
However, these two methods have both advantages and disadvantages at the present time.
In the SIMOX method, the uniformity of thickness of the SOI film is excellent, but in contrast the sharpness of the interface with a buried oxide film is poor, so there remain problems in operating performance, reliability, etc. of the transistor.
On the other hand, an SOI substrate prepared by the wafer bonding method has good characteristics at the buried oxide film interface, but is a complicated process and, in addition, since the SOI film is made thin by polishing, suffers from a problem in controllability of the SOI film thickness if the precision of detection of the end point of the polishing is poor.
The wafer bonding method includes a case where the SOI layer is formed on the entire surface and a case where the SOI layer is separated in the planar direction to form isolated patterns. In the latter case, it is possible to provide a step difference at the substrate to be polished before bonding and use the layer of the insulator (separation region in the plane direction) filled in the depressions as a stop for the detection of the end point of the polishing.
The flow of the process for fabrication of an SOI substrate common to these methods roughly comprises the following four steps:
(a) Planarization and surface treatment of the bonding surfaces
(b) Bonding and annealing
(c) Grinding
(d) Polishing (or selective polishing)
In an SOI substrate prepared in this way, not only can the thickness etc. of the buried insulating film be relatively freely set, but it also becomes possible to form elements and interconnect them on parts to become the active layer of the substrate that can be polished before bonding, and then bury them in the insulating film in advance so as to prepare an LSI having a high degree of integration in which elements are three dimensionally arranged on the two sides of the active layer in the thickness direction.
Further, when fabricating a MOSFET, it is possible to form, buried in the insulating film, not only the front side gate electrode arranged on the front surface side of the silicon active layer via the gate insulating film, but also a second gate electrode. This insulating film buried type gate electrode will be referred to as a “back side gate electrode.”When using the front side gate electrode for signal input, the short channel effect can be suppressed by control from this back side gate electrode, and the threshold voltage, swing width, or gain of the transistor can be controlled. Further, application to an X-MOS (also referred to as a “double gate MOS”) using both of the front side gate and the back side gate for signal input to achieve a 2-channel mode transistor becomes possible.
When supplying a bias voltage to the back side gate electrode, in the past there was only the fixed bias method of applying a constant voltage. In recent years the technique of controlling (changing) the bias voltage to be supplied to the back side gate electrode so as to improve the transistor characteristics has been proposed.
With a transistor referred to as a “dynamic Vth MOS” employing this bias application method, the value of the voltage supplied to the back side gate electrode is dynamically controlled according to the input signal, making the threshold voltage Vth relatively high and reduce the leakage current when the transistor is off, and making the threshold voltage Vth relatively low and improve the drive capability when the transistor is on.
Accordingly, if using this “dynamic Vth” technique, the power supply voltage can be reduced without lowering the operating speed of the transistor and then the leakage current during stand-by can be reduced to enable a reduction of the power consumption of the semiconductor device using the related transistor for an active element.
FIG. 12
shows a sectional view of the principal parts of a semiconductor device of the configuration of the related art. This
FIG. 12
shows two transistors having different operation modes, that is, a “dynamic Vth MOS transistor” (hereinafter referred to as a “DV-MOS”) and a MOS transistor of in a conventional operation mode (hereinafter referred to as a “CON-MOS”).
In a semiconductor device
100
shown in
FIG. 12
, an insulating layer
103
is formed on a supporting substrate
101
via a bonding layer
102
.
At the surface side in the insulating layer
103
are formed a silicon active layer
104
for the CON-MOS and a silicon active layer
105
for the DV-MOS separated from each other. Predetermined impurities are added to the silicon active layers
104
and
105
with a relatively low concentration.
In the insulating layer
102
are buried a back side gate electrode
107
facing a bottom surface of the CON-MOS silicon active layer
104
via a back side gate insulating film
106
, and a back side gate electrode
109
facing a bottom surface of the DV-MOS silicon active layer
105
via a back side gate insulating film
108
separated from each other. The back side gate insulating films
106
and
108
are made of silicon oxide films having the same thickness. Further, the back side gate electrodes
107
and
109
are made of polycrystalline silicon and doped with predetermined impurities with a relatively high concentration.
On the silicon active layer
104
or
105
is formed a gate electrode
111
of the transistor via a front side gate insulating film
110
. Further, on the front surface side in the silicon active layers
104
and
105
, though not illustrated, are formed source and drain impurity regions having an LDD structure. An inter-layer insulating film
112
is deposited over the entire surface, the inter-layer insulating film
112
is partially etched through, plugs
113
are buried there, and an interconnection layer
114
is formed thereon.
Summarizing the problems to be solved by the invention, in the semiconductor device
100
of the related art, however, when forming an integrated circuit by mixing the two types of MOSFETs (CON-MOS and DV-MOS) having different operating modes, there was the problem that the electric characteristics of this circuit did not sufficiently draw out the best performances of the transistors.
This is due to the fact that the two types of transistors with the different operation modes each have their own advantages and disadvantages in
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