Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-19
2002-05-14
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06389583
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to an output circuit capable of adjusting an electrostatic breakdown voltage and a driving current.
2. Description of the Related Art
The circuit configuration of a general output circuit is shown in FIG.
7
.
The output circuit
1
as shown in
FIG. 7
includes protective transistors for dealing with electrostatic breakdown (a P-channel protective transistor P
2
on a VDD side and an N-channel protective transistor N
2
on a VSS side) and output transistors (a P-channel output transistor P
1
on the VDD side and an N-channel output transistor on the VSS side).
In such a circuit configuration, in order to deal with the electrostatic breakdown, as shown in
FIG. 7
, there are provided the P-channel protective transistor P
2
on the VDD side and the N-channel protective transistor N
2
on the VSS side.
Since the electrostatic breakdown strength is correlated with the cell size (or transistor size) of each of the protective transistors P
2
and N
2
, in order to provide a desired electrostatic breakdown strength, the cell size must be changed (Actually, the total size of the protective transistors P
2
, N
2
and output transistors P
1
, N
1
is adjusted).
FIG. 8
is a pattern lay-out diagram of a portion of the output circuit
1
as shown in FIG.
7
. For simplicity of illustration, only regions are shown which correspond to the N-channel output transistor N
1
and the N-channel protective transistor N
2
both of which are located on the VSS side. Incidentally, the pattern layout of the regions corresponding to the P-channel output transistor P
1
and the P-channel protective transistor P
2
is configured in the same manner (a grounding potential line VSS is substituted for a power potential line VDD.
In
FIG. 8
, GP
1
and GP
2
denote gate electrodes made of e.g. a polycrystalline silicon film. The gate electrode GP
1
of the N-channel output transistor N
1
on the VSS side is connected to an input (IN) terminal, whereas the gate electrode GP
2
of the P-channel protective transistor N
2
on the VSS side is connected to the grounding potential line VSS.
In
FIG. 8
, M
1
and M
2
denote metallic wirings of e.g. aluminum. The metallic wiring M
1
connected with an output (OUT) terminal is in contact with the respective drain regions of the above N-channel output transistor N
1
and N-channel protective transistor N
2
through contact holes C
1
. The metallic wiring M
2
connected to the grounding potential line VSS is in contact with the respective source regions and guard band regions
2
of the above N-channel output transistor N
1
and N-channel protective transistor N
2
through contact holes C
2
.
In the microcomputer or logic LSI using such an output circuit
1
developed in recent years, as the case may be, different output currents are required for both the P-channel output transistor P
1
and the N-channel output transistor N
1
in accordance with a user's request (In this case, for example, the transistor size is increased to increase the output current). Further, the rising or falling speed in an oscillator (OSC) circuit may seriously affect a car audio set or unit so that noise occurs to impair the reliability of the audio set (In this case, the transistor size is reduced to prevent noise from occurring).
Thus, the transistor size of the output transistors P
1
and N
1
must be adjusted to optimum size. For this purpose, the design of a plurality of mask layers (three sheets of GP, C and M described above) must be changed. Correspondingly, a plurality of photomasks must be created again.
This disadvantageously increases the man-hours of designing the integrated circuit and of making the photomasks.
SUMMARY OF THE INVENTION
An object of the present invention is provide a method of pattern-layout of semiconductor device capable of easily changing the sizes of a protective transistor and output transistor in order to deal with electrostatic breakdown.
Another object of the present invention is to provide a semiconductor device formed by the method of pattern-layout of.
In order to attain the above objects, (for example as shown in FIG.
1
,) a semiconductor device according to a first embodiment of the present invention comprises an N-channel output transistor N
1
(or P-channel output transistor P
1
) having a first gate electrode GP
11
(A, B) which is formed to surround contact holes C
11
formed in its drain region so as to be in contact with a first wiring M
11
connected to an output (OUT) terminal, and is connected to an input (IN) terminal; and
an N-channel protective transistor N
2
(or P-channel output transistor P
2
) for dealing with electrostatic breakdown having a second gate electrode GP
12
(A, B) which is formed to surround contact holes C
12
formed in its drain region so as to be in contact with a second wiring M
12
connected to a grounding potential line VSS (or power potential line VDD) and is connected to the grounding potential line, and characterized in that an pitch of the contact holes C
11
is wider than that of contact holes formed in a source region of each said transistors.
In such a configuration, by changing the number of the contact holes C
11
, C
12
surrounded by the gate electrodes GP
11
(A, B) and GP
12
(A, B), the transistor size of each of the N-channel output transistor N
1
and N-channel protective transistor N
2
(or P-channel output transistor P
1
and P-channel protective transistor P
2
).
Further, a pattern layout method for such as transistor composed of a protective transistor (P
2
or N
2
) for dealing with electrostatic breakdown and an output transistor (P
1
or N
1
) is characterized in that a transistor size of each of said protective transistor and said output transistor is changed within a total size of both transistors (P
1
+P
2
) or (N
1
+N
2
).
The patter layout method is characterized in that a design change incident to a change in the transistor size of said transistors is made by only replacing a mask layer for forming the gate electrodes.
A semiconductor device according to the second embodiment of the present invention is characterized in that the pitch of a contact holes C
11
is wider than that of the contact holes C
2
, and in that the transistor size of each of the N-channel output transistor and N-channel protective transistor (or P-channel output transistor and P-channel protective transistor) can be finely adjusted according to a position where an element isolation film F
21
(or F
31
) is formed as shown in FIG.
6
.
The pattern layout method for the semiconductor device is characterized in that the transistor size of each of the protective transistor (P
2
or N
2
) for dealing with electrostatic breakdown and output transistor (P
1
or N
1
) is fined adjusted by the position where the element isolation film F
21
(or F
31
) is formed.
The patter layout method is characterized in that a design change incident to a change in the transistor size of said transistors is made by only replacing a mask layer for forming the element isolation film (F).
In accordance with the present invention, the transistor size of each of the protective transistors P
2
, N
2
and output transistors P
1
, N
1
for dealing with the electrostatic breakdown due to the requirement from a user and improvement in the characteristic can be made by only replacing a sheet of the mask layer for forming the gate electrode (GP). This greatly contributes the man-hours of designing an integrated circuit and manufacturing photomasks.
Further, the fine adjustment of the transistor size of each of the protective transistors P
2
, N
2
and output transistors P
1
, N
1
for dealing with the electrostatic breakdown due to the various requirements from users and improvement in the characteristic can be made by only replacing a sheet of the mask layer for forming the element isolation film. This greatly contributes the man-hours of designing an integrated circuit and manufacturing photomasks.
The a
Do Thuan
Fish & Richardson P.C.
Sanyo Electric Co,. Ltd.
Smith Matthew
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