Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-11-28
2004-03-09
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S691000, C257S778000, C257S303000, C257S758000, C257S700000, C257S532000, C257S738000
Reexamination Certificate
active
06703705
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a decoupling capacitor which suppresses or compensates a momentary drop in direct current voltage occurring at the time of a load variation in an LSI device operating at a high speed.
2. Related Art
FIG. 24
of the accompanying drawings shows a variation (&Dgr;V) in the DC voltage V supplied to an LSI device
104
in the case in which the LSI device
104
, which performs high-speed switching with a rise time of t
1
, is mounted to a circuit board
111
. In
FIG. 24
, there is no decoupling capacitor mounted, which suppresses or compensates for a voltage variation &Dgr;V in the DC voltage supplied to the circuit board
111
. The reference numeral
101
in
FIG. 24
denotes a power supply line,
102
is a signal line,
103
is a ground line,
105
is a DC power supply, and
106
are vias and through holes.
FIG. 25
is the equivalent circuit of FIG.
24
. When the LSI device
104
is switched at a high speed, the wiring between the DC power supply
105
and the LSI device
104
, or the parasitic inductance L (L
1
+L
2
+L
3
+L
4
+L
5
+L
6
)
108
existing in the vias or through holes
106
cause a variation in the DC voltage V supplied to the LSI device
104
. When this occurs, the amount of variation &Dgr;V (voltage drop) in the DC voltage is given by the equation (1).
&Dgr;V=
R×&Dgr;i+L×di/dt
(1)
In the above, R is the resistance and L is the inductance of the wiring and the capacitor, and &Dgr;i is the current variation over the time &Dgr;t.
Therefore, the larger are the resistance R, the wire, the parasitic inductance L
108
existing in the via or through hole, or the load variation di, or the smaller is the variation time dt, the greater will be the increase in the voltage variation &Dgr;V. In recent years, LSI device is driven at high frequency the clock rates of which having come to exceed several hundred megahertz. The rise time t
r
of a pulse waveform in a digital circuit is thus equivalent to the load variation time dt. The faster is the clock frequency, the shorter is the rise time t
r
, so that the greater is the amount of voltage variation &Dgr;V. In addition to this effect, recent years have seen advancements in the reduction of the input voltage V in order to achieve LSI devices that operate at high speeds (for example, reduction from 3.3 V to 1.8 V), and there is a trend toward even greater increases in the voltage variation rate (&Dgr;V/V), so that the value of &Dgr;V/v exceeds the allowable value for an LSI device (approximately 5%). While no problem would arise if a switching power supply were to be able to compensate for this voltage variation, because a switching power supply requires from 100 ns to several &mgr;s of time in order to perform compensation, it cannot track the voltage variations encountered in an LSI device that is switched at a high speed (several hundred ps to 1 ns).
In order to prevent misoperation in a LSI device such as this caused by voltage variations, in the past a capacitor was connected in parallel between the power supply line and the ground line, this capacitor generally being referred to as a decoupling capacitor. A decoupling capacitor has two effects, the effect of bypassing a high-speed switching signal generated from the LSI device, shortening the path of a high-speed signal, and reducing the parasitic inductance (which will be referred to as the first effect hereinafter), and the effect of supplying the load from the decoupling capacitor (that is, discharging thereinto) so as to compensate for the voltage drop occurring temporarily when performing high-speed switching (which will be referred to as the second effect hereinafter). In accordance with Equation (1), in order to make &Dgr;V small, the inductance L (in, for example, the wiring and the via and through holes) can be minimized, and recently in order to minimize this inductance, as shown in
FIG. 26
, a decoupling capacitor
109
is mounted directly to the side of the LSI device
104
, or directly below the LSI device
104
via the intervening circuit board
111
.
FIG. 27
shows the equivalent circuit for this arrangement. By virtue of the first and second effects achieved by the decoupling capacitor, the amount of variation &Dgr;V in the DC voltage supplied to the LSI device is reduced, as shown by the broken lines in the graph at the upper part of FIG.
27
.
The main cause of an increase in the variation of the DC voltage supplied to an LSI device that switches at a high speed is parasitic inductance L existing in the wiring path between the LSI device and the decoupling capacitor. This parasitic inductance L is the parasitic inductance existing in wiring, a via hole, and a through hole. The parasitic inductance of the decoupling capacitor itself is yet another cause of voltage variation. In order to reduce the parasitic inductance of wiring, a via hole, and a through hole, it is necessary to make the lengths thereof be as small as possible. However, with a capacitor mounted in the vicinity of an LSI device, because there is a parasitic inductance of approximately 100 pH/mm in wiring, vias, and through holes, if we consider wiring lengths and the sizes of vias and through holes in the past, there would be a parasitic inductance of approximately 300 pH. Additionally, it is not possible to ignore the parasitic inductance of the decoupling capacitor itself (which, in the past, has been approximately 1 nH for each chip capacitor, so that if N capacitors are connected in parallel, the total effective parasitic inductance would be 1 nH/N). Because of the existence of these parasitic inductances, if we consider the case of a DC supply voltage of 1.8 V and high-speed switching equivalent to 500 MHz, the voltage variation rate &Dgr;V/v would be at least approximately 10 to 15%, this representing the cause of misoperation of the LSI device.
Additionally, in the past the resonant frequency of a decoupling capacitor was low, this being in the range from several tens of MHz to 80 MHz, there was the problem that the decoupling capacitor failed to function effectively as a decoupling capacitor when the LSI device clock frequency reached over several hundred MHz, so that there was a need to make the resonant frequency of the decoupling capacitor itself higher (because a high-speed signal of a frequency higher than the resonant frequency of the decoupling capacitor resulted in a lag that prevented the proper tracking for load compensation, thereby making it impossible to effectively suppress voltage variation). In order to achieve a high resonant frequency in a capacitor, it is necessary to reduce the parasitic inductance of the decoupling capacitor itself, making it necessary to take measures with regard to such structural features as the shape of the capacitor electrodes and the electrolytic thickness and the like. According to Nikkei Electronics (Apr. 19, 1999 edition), pp. 144-156, it is known that reducing the electrolytic thickness reduces the parasitic inductance, and an invention related to a semiconductor device using a thin-film capacitor has been reported (for example, in Japanese unexamined patent publications (KOKAI) No. 11-458822 and 8-97360).
If we take the case of an LSI device (A) having a clock frequency f
H
of 100 MHz, a maximum current consumption I of 10 A, and a power supply voltage V of 3.3 V, and an LSI device (B) for which f
H
=500 MHz, I=90 A and V=1.8 V, if a calculation is performed of the capacitance C of a decoupling capacitor required to compensate for the voltage drop &Dgr;V (assumed to be 10% of the rated voltage) during one clock cycle, because the electrical charge Q required to compensate for the voltage drop is Q=C×&Dgr;V=I×(1/f
H
), from the relationship of
C=I
/(
f
H
×&Dgr;V) (2)
the required capacitance C in the case of the LSI device (A) would be 10 A/(100×10
6
×3.3×0.1)=
Mori Toru
Shibuya Akinobu
Shimada Yuzo
Yamamichi Shintaro
Yamazaki Takao
Greene Pershelle
NEC Corporation
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