Multi-valued logical circuit with less latch-up

Details Multi-valued logical circuit with less latch-up Multi-valued logical circuit with less latch-up

2002-06-21

2004-03-02

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Three or more active levels

C326S060000

Reexamination Certificate

active

06700406

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-valued logical circuit, and particularly to a multi-valued logical circuit which outputs one of a plurality of power supply potentials and a reference potential to an output node in response to a plurality of input signals.
2. Description of the Background Art
A multi-valued logical gate which outputs a logical level other than “H” and “L” levels in addition to a binary logical circuit which outputs an “H” or “L” level is conventionally mounted on a semiconductor integrated circuit.
FIG. 10
is a circuit diagram which shows a conventional three-valued inverter. In
FIG. 10
, this three-valued inverter includes P-channel MOS transistors
31
and
32
and an N-channel MOS transistor
33
. P-channel MOS transistor
31
is connected between the line of a first power supply potential VDD (e.g., 3.0V) and an output node N
31
and the gate thereof receives a signal VA. P-channel MOS transistor
32
is connected between the line of a second power supply potential VDD′ (e.g., 3.5V) and output node N
31
and the gate thereof receives a signal VB. N-channel MOS transistor
33
is connected between output node N
31
and the line of a ground potential VSS (
0
V) and the gate thereof receives a signal VC. The back gates of P-channel MOS transistors
31
and
32
are both connected to the line of second power supply potential VDD′.
FIG. 11
is a view which shows the operation of the three-valued inverter shown in FIG.
10
. In
FIG. 11
, in a state
1
, the potentials of signals VA, VB and VC are set at ground potential VSS, second power supply potential VDD′ and ground potential VSS, respectively. As a result, P-channel MOS transistor
31
becomes conductive, P-channel MOS transistor
32
and N-channel MOS transistor
33
become nonconductive and the potential of an output signal VO becomes first power supply potential VDD.
In a state
2
, the potentials of signals VA, VB and VC are set at second power supply potential VDD′, ground potential VSS and ground potential VSS, respectively. As a result, P-channel MOS transistor
32
becomes conductive, P-channel MOS transistor
31
and N-channel MOS transistor
33
become nonconductive and the potential of output signal VO becomes second power supply potential VDD′.
In a state
3
, the potentials of signals VA, VB and VC are all set at second power supply potential VDD′. As a result, P-channel MOS transistors
31
and
32
become nonconductive, N-channel MOS transistor
33
becomes conductive and the potential of output signal VO becomes ground potential VSS. It is noted that the same result can be obtained even if the potentials of signals VA and VB are both set at second power supply potential VDD′ and the potential of signal VC is set at first power supply potential VDD. As can be seen, this three-valued inverter can selectively output one of the three logical levels of first power supply potential VDD, second power supply potential VDD′ and ground potential VSS.
FIG. 12
is a circuit diagram which shows the configuration of another conventional three-valued inverter. Referring to
FIG. 12
, this three-valued inverter differs from that shown in
FIG. 10
in that P-channel MOS transistor
31
is replaced by an N-channel MOS transistor
34
. That is, N-channel MOS transistor
34
is connected between the line of first power supply potential VDD and output node N
31
and the gate thereof receives signal VA.
FIG. 13
is a view which shows the operation of the three-valued inverter shown in FIG.
12
. In
FIG. 13
, in state
1
, the potentials of signals VA, VB and VC are set at second power supply potential VDD′, second power supply potential VDD′ and ground potential VSS, respectively. As a result, N-channel MOS transistor
34
becomes conductive, P-channel MOS transistor
32
and N-channel MOS transistor
33
become nonconductive and the potential of output signal VO becomes first power supply potential VDD.
In state
2
, the potentials of signals VA, VB and VC are all set at ground potential VSS. As a result, P-channel MOS transistor
32
becomes conductive, N-channel MOS transistors
34
and
33
become nonconductive and the potential of output signal VO becomes second power supply potential VDD′.
In state
3
, the potentials of signals VA, VB and VC are set at ground potential VSS, second power supply potential VDD′ and second power supply potential VDD′, respectively. As a result, N-channel MOS transistor
33
becomes conductive, N-channel MOS transistor
34
and P-channel MOS transistor
32
become nonconductive and the potential of output signal VO becomes ground potential VSS. It is noted that the same result can be obtained even if the potentials of signals VA, VB and VC are set at ground potential VSS, second power supply potential VDD′ and first power supply potential VDD, respectively.
Meanwhile, in case of the three-valued inverter shown in
FIG. 10
, not first power supply potential VDD but second power supply potential VDD′ is applied to the back gate of P-channel MOS transistor
31
for the following reason. If first power supply potential VDD is applied to the back gate of P-channel MOS transistor
31
, the potential of the drain of P-channel MOS transistor
31
becomes second power supply potential VDD′, the PN junction between the drain and the back gate of P-channel MOS transistor
31
is directed in a forward direction and high current is carried to thereby cause latch-up in state
2
shown in FIG.
11
. It is noted that P-channel MOS transistor
31
is constituted, as shown in
FIG. 14
, so that a gate electrode
31
g
is formed on the surface of an N type substrate
35
through a gate insulating film
31
i
and a P type source region
31
s
and a P type drain region
31
d
are formed on one side and the other side of gate electrode
31
g
, respectively. Gate electrode
31
g
, source region
31
s
, drain region
31
d
and N type substrate
35
become the gate, source, drain and back gate of P-channel MOS transistor
31
, respectively.
In the three-valued inverter shown in
FIG. 10
, however, different power supply potentials VDD and VDD′ are applied to the source and the back gate of P-channel MOS transistor
31
, respectively. Due to this,if power supply potentials VDD and VDD′ become VDD>VDD′ in a transient period before power supply potentials VDD and VDD′ reach normal potentials during a power-up period or the like, the PN junction between the source and the back gate of P-channel MOS transistor
31
is directed in the forward direction and latch-up may possibly occur.
On the other hand, in the three-valued inverter shown in
FIG. 12
, since P-channel MOS transistor
31
is replaced by N-channel MOS transistor
34
, latch-up does not occur during a power-up period described above. However, in state
1
shown in
FIG. 13
, the potential of the drain of N-channel MOS transistor
31
becomes first power supply potential VDD=3V, the potential of the gate thereof becomes second power supply potential VDD′=3.5V and N-channel MOS transistor
34
is source-follower connected. Due to this, the potential of the source of N-channel MOS transistor
34
, i.e., the potential of output signal VO cannot be higher than a potential VDD′=Vth obtained by subtracting the threshold voltage Vth of N-channel MOS transistor
34
from gate potential VDD′ of N-channel MOS transistor
34
. If threshold voltage Vth is, for example, not higher than 0.5V, the potential of output signal VO becomes VO=VDD=3V. However, if threshold voltage Vth is higher than 0.5V, the potential of output signal VO becomes VO=VDD′−Vth<VDD=3V, i.e., lower than VDD.
SUMMARY OF THE INVENTION
It is, therefore, the main object of the present invention to provide a multi-valued logical circuit wherein no latch-up occurs and an output potential is not lowered by as much as the thresh

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