Semiconductor device and method for operating the same

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

Reexamination Certificate

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C326S115000, C327S210000, C327S214000

Reexamination Certificate

active

08035420

ABSTRACT:
A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.

REFERENCES:
patent: 6275880 (2001-08-01), Quinlan et al.
patent: 7777521 (2010-08-01), Hanna et al.
patent: 2008/0129329 (2008-06-01), Marsh et al.
patent: 2008/0144760 (2008-06-01), Song et al.
patent: 2008/0237512 (2008-10-01), Lin
patent: 2009/0174455 (2009-07-01), Dimitriu et al.
M. Jeeradit et al., “Characterizing Sampling Aperture of Clocked Comparators”, 2008 Symposium on VLSI Circuits Digest of Technical Papers, pp. 68-69.

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