Semiconductor device and method for mitigating electrostatic...

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07606046

ABSTRACT:
A semiconductor device including a PCB including conductive patterns formed on at least one surface of the PCB, external connection terminals including at least one ground terminal and coupled to the conductive patterns, at least one semiconductor chip mounted on a surface of the PCB, and an ESD protection pattern being coupled to at least one of the least one ground terminal, the at least one ground terminal not being coupled to the conductive patterns. A semiconductor memory device, including a PCB, a memory chip mounted on a first surface of the PCB, external connection terminals formed on a second surface of the PCB, and a first ESD protection pattern being coupled to at least one ground terminal. A method of mitigating ESD in a semiconductor device, including mounting a chip on a PCB, forming conductive patterns on the PCB, and forming at least one ESD protection pattern on the PCB, the ESD protection pattern being connected to a ground terminal and not being coupled to the conductive patterns.

REFERENCES:
patent: 5552951 (1996-09-01), Pasch et al.
patent: 5644167 (1997-07-01), Weiler et al.
patent: 5796570 (1998-08-01), Mekdhanasarn et al.
patent: 5889308 (1999-03-01), Hong et al.
patent: 6064094 (2000-05-01), Intrater et al.
patent: 6249413 (2001-06-01), Duvvury
patent: 6433394 (2002-08-01), Intrater
patent: 2004/0095699 (2004-05-01), Kohno
patent: 2000-049429 (2000-02-01), None
patent: 2001-0018947 (2001-03-01), None
patent: 2001-0018949 (2001-03-01), None
patent: 1020010018949 (2001-03-01), None
Korean Office Action.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device and method for mitigating electrostatic... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and method for mitigating electrostatic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for mitigating electrostatic... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4107063

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.