Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-01-25
2011-01-25
Blum, David S (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S199000, C257SE21632, C257SE27062
Reexamination Certificate
active
07875935
ABSTRACT:
A semiconductor device includes a silicon substrate; an N-channel field-effect transistor including a first gate insulating film on the silicon substrate, a first gate electrode on the first gate insulating film and a first source/drain region; and a P-channel field-effect transistor including a second gate insulating film on the silicon substrate, a second gate electrode on the second gate insulating film and a second source/drain region. Each of the first and second gate electrodes includes a crystallized nickel silicide region containing an impurity element, the crystallized nickel silicide region being contact with the first or second gate insulating film, and a barrier layer region in an upper portion including an upper surface of the gate electrode, the barrier layer region containing an Ni diffusion-preventing element higher in concentration than that of a lower portion below the upper portion.
REFERENCES:
patent: 6599831 (2003-07-01), Maszara et al.
patent: 2005/0070062 (2005-03-01), Visokay et al.
patent: 2006/0084247 (2006-04-01), Liu
patent: 2005-129551 (2005-05-01), None
patent: 2005-524243 (2005-08-01), None
patent: 2005-252192 (2005-09-01), None
patent: 2005-294360 (2005-10-01), None
patent: 2006-108355 (2006-04-01), None
patent: 2006-147828 (2006-06-01), None
patent: 2006-196646 (2006-07-01), None
patent: WO 03/094243 (2003-11-01), None
patent: WO 2006/001271 (2006-01-01), None
Pawlak et al. “Modulation of the Workfunction of Ni Fully Silicided Gates by Doping: Dielectric and Silicide Phase Effects” : IEEE Electron Device Letters, vol. 27, No. 2 (Feb. 2006), p. 99-101, full text, Figs. 1 to 3.
Oh et al. “Novel Nitrogen Doped Ni Self-Alingned Silicide Process for Nanoscale Complementary Metal Oxide Semiconductor Technology” : Jpn. J. Appl. Phys., vol. 44, No. 4B (2005), pp. 2142-2146, full text, Figs. 1 to 9.
Nobuyuki Mise et al., “Chisso O Tenka shita Ni Spatter ni yoru Epitaxial NiSi2 no Teion Keisei” : Dai 53 Kai Oyo Butsurigaku Kankei Rengo Koenkei Koen Yokoshu No. 2 (Mar. 22, 2006), p. 929.
JaeHoon Lee et al., “Tunable Work Function Dual Metal Gate Technology for Bulk and Non-Bulk CMOS”, International Electron Devices Meeting Technical Digest 2002, p. 359.
Hwa Sung Rhee, et al., “Negative Bias Temperature Instability of Carrier-Transport Enhanced pMOSFET with Performance Boosters”, International Electron Devices Meeting Technical Digest 2005, p. 709.
Blum David S
McGinn IP Law Group PLLC
NEC Corporation
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