Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-01-14
2001-10-02
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S670000, C257S676000, C257S696000, C257S700000, C257S787000, C438S106000, C438S111000, C438S112000
Reexamination Certificate
active
06297544
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and, particularly, to an effective technology for application in a semiconductor device having signal leads and power supply leads on a semiconductor chip.
BACKGROUND ART
There is available a semiconductor device in which a semiconductor chip having a circuit system mounted there on is sealed with a resin sealer. In this semiconductor device, the die pad (also called “tub”) of a lead frame is omitted and an LOC (Lead On Chip) structure or a COL (Chip On Lead) structure which can be used for large-sized chips is employed. An LOC structure semiconductor device is disclosed by Japanese Patent Laid-open No. Hei 2-246125 (laid open on Oct. 1, 1990), for example. A COL structure semiconductor device is disclosed by Thesis No. ICD 89-103 of the technical research report of the Denshi Joho Tsushin Gakkai published in March, 1989.
The above LOC structure semiconductor device is constituted such that leads are fixed on the main surface (circuit formed surface) of a semiconductor chip through an insulating film. The insulating film has an adhesive layer formed of a polyimide-based resin on both sides (front and rear sides) of a resin substrate made from a polyimide-based resin. Since this insulating film easily absorbs water, water absorbed by the insulating film is vaporized and expanded with heat at the time of a temperature cycle test which is an environment test for a semiconductor device and heat when a semiconductor device is mounted, thereby causing the cracking of a resin sealer (package cracking).
An attempt is then made to arrange leads on the main surface of a semiconductor chip by eliminating the insulating film. This technology is disclosed by Japanese Patent Laid-open No. Hei 8-274234 (laid open on Oct. 18, 1996), for example.
A semiconductor chip having a circuit system mounted thereon has such a structure that a multi-layer wiring layer which consists of a plurality of wiring layers and a plurality of interlayer insulating layers is formed on a semiconductor substrate and a surface protective film (final protective film) is formed on the multi-layer wiring layer. Power source wires for supplying an operation potential (Vcc) and a reference potential (Vss) to transistor elements constituting the circuit system are formed in each wiring layer of the multi-layer wiring layer. Further, signal wires for connecting the transistor elements are formed in each wiring layer. The power source wires and the signal wires are electrically connected to respective external terminals for power source and respective external terminals for signals formed on the uppermost wiring layer of the multi-layer wiring layer.
Meanwhile, power supply leads electrically connected to the external terminals for power source by wires and signal leads electrically connected to the external terminals for signals by wires are formed on the main surface of the semiconductor chip. Floating capacitance (parasitic capacitance) is applied to the power supply leads and the signal leads because the power supply leads and the signal leads are formed on the power source wires formed in the multi-layer wiring layer of the semiconductor chip through the surface protective film and an insulator such as the insulating film. Floating capacitance applied to the power supply leads is preferably large in order to prevent fluctuations in power source potential caused by switching noise. Parasitic capacitance applied to the signal leads is preferably small in order to increase the signal propagation speed.
However, as the power supply leads and the signal leads are situated on the same plane on the main surface of the semiconductor chip, floating capacitance applied to the power supply leads and floating capacitance applied to the signal leads are the same, whereby the prevention of fluctuations in power source potential and the acceleration of the signal propagation speed cannot be carried out at the same time, thereby preventing improvement on the electric characteristics of the semiconductor device. Particularly when the insulating film is eliminated and leads are fixed on the main surface of the semiconductor chip through an adhesive material, floating capacitance applied to the power supply leads and the signal leads become large, which is preferred for the prevention of fluctuations in power source potential but not preferred for the acceleration of the signal propagation speed.
It is an object of the present invention to provide a technology which can improve the electric characteristics of a semiconductor device.
The above and other objects and new features of the present invention will become apparent from the following description when taken into conjunction with the accompanying drawings.
DISCLOSURE OF THE INVENTION
Overviews of representatives of the present invention disclosed in this specification are described briefly as follows.
(1) There is provided a semiconductor device having power supply leads and signal leads on the main surface of a semiconductor chip, wherein the interval between the signal leads and the semiconductor chip is made larger than the interval between the power supply leads and the semiconductor chip. The signal leads are separated from the semiconductor chip and the power supply leads are fixed to the main surface of the semiconductor chip. Further, the power supply leads are fixed to the main surface of the semiconductor chip directly or through an adhesive layer.
A surface protective film is formed on the main surface of the semiconductor chip and power source wires electrically connected to the power supply leads are formed under the surface protective layer.
The power supply leads and the signal leads are electrically connected to respective external terminals arranged on the main surface of the semiconductor chip, the semiconductor chip, the inner portions (inner leads) of the power supply leads, the inner portions of the signal leads and the wires are sealed by a resin sealer, and the outer portions (outer leads) of the power supply leads and the signal leads are drawn outside the resin sealer.
(2) There is provided a semiconductor device comprising:
a rectangular semiconductor chip having a plurality of semiconductor elements and a plurality of external terminals on the main surface, the plurality of external terminals being arranged in a longitudinal direction;
first leads and second leads, each having inner portions and outer portions, parts of the inner portions being arranged on the main surface of the semiconductor chip, and the end portions of the inner portions being arranged near the plurality of external terminals and electrically connected to the plurality of external terminals; and
a rectangular resin sealer for sealing the semiconductor chip and the inner portions of the first leads and the second leads, whose long sides extend along the long sides of the semiconductor chip and whose short sides extend along the short sides of the semiconductor chip, wherein
the outer portions of the first leads and the second leads project from the long sides of the resin sealer;
the inner portions of the first leads and the second leads extend over the short sides of the semiconductor chip and lie on the main surface of the semiconductor chip;
the distance between parts of the inner portions of the second leads lying on the main surface of the semiconductor chip and the main surface of the semiconductor chip is larger than the distance between parts of the inner portions of the first leads lying on the main surface of the semiconductor chip and the main surface of the semiconductor chip; and
the first leads are connected to fixed potential terminals out of the plurality of external terminals and the second leads are connected to signal terminals out of the plurality of external terminals.
Since floating capacitance applied to the power supply leads can be made large and floating capacitance applied to the signal leads can be made small by the above means, the prevention of fluctuations in power source potential and
Katagiri Mitsuaki
Masuda Masachika
Nakamura Atsushi
Nishimura Asao
Tsubosaki Kunihiro
Hitachi , Ltd.
Keshavan B. V.
Mattingly Stanger & Malur, P.C.
Smith Matthew
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