Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
1999-09-20
2001-11-06
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S737000, C257S738000, C257S759000, C257S773000, C257S780000, C257S787000, C257S792000, C257S793000
Reexamination Certificate
active
06313532
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device, for use in information communication equipment and office electronic equipment, applicable to high density packaging, containing a semiconductor integrated circuit unit and including wires and the like to be connected with external terminals, and a method for manufacturing the semiconductor device.
BACKGROUND ART
In accordance with recent development of compact and high level function electronic equipment, a semiconductor device including a semiconductor integrated circuit unit is also required of compactness, high packaging density and high speed in packaging work. For example, as memory packages, an LOC (lead on chip), a SON (small outline non-lead), a &mgr;BGA (micro-ball grid array) using a TAB tape (disclosed in National Publication of translated version No. 06-504408) and the like have been developed.
Now, a conventional semiconductor device designated as &mgr;BGA and a method for manufacturing the device will be described with reference to drawings.
FIG. 10
is a sectional view of the conventional semiconductor device designated as &mgr;BGA. In
FIG. 10
, a reference numeral
101
denotes a semiconductor chip including semiconductor elements, a reference numeral
102
denotes a wiring circuit sheet of flexible sheet formed on the semiconductor chip
101
, a reference numeral
103
denotes a flexible low elasticity material disposed between the semiconductor chip
101
and the wiring circuit sheet
102
, a reference numeral
104
denotes a partial lead corresponding to a part of a wiring layer, a reference numeral
105
denotes an element electrode electrically connected with the semiconductor element included in the semiconductor chip
101
, and a reference numeral
106
denotes an electrode formed on the surface of the wiring circuit sheet
102
for attaining electric connection with an external device.
As is shown in
FIG. 10
, in the conventional semiconductor device designated as &mgr;BGA, the wiring circuit sheet
102
is formed on the semiconductor chip
101
with the low elasticity material
103
sandwiched therebetween, and the element electrode
105
on the semiconductor chip
101
is electrically connected with the electrode
106
on the wiring circuit sheet
102
through the partial lead
104
.
Next, the method for manufacturing the aforementioned conventional semiconductor device will be described with reference to the same drawing.
First, the wiring circuit sheet
102
in the shape of flexible sheet is adhered onto the semiconductor chip
101
with the low elasticity material
103
sandwiched therebetween. The wiring circuit sheet
102
includes a wiring pattern therein, the electrode
106
to be connected with the wiring pattern is formed on the wiring circuit sheet
102
, and the partial lead
104
extends from the electrode
106
. In this case, the low elasticity material
103
is an insulating material having an adhesive function.
Next, the partial lead
104
and the element electrode
105
are electrically connected with each other by using a conventional thermo compression bonding technique generally used in “TAB” (tape automated bonding) or an ultrasonic bonding technique. In this manner, the semiconductor device is manufactured.
Specifically, owing to the aforementioned structure of the semiconductor device, the semiconductor device can be electrically connected with external equipment through a large number of electrodes
106
two-dimensionally formed on the wiring circuit sheet
102
, while suppressing stress. Accordingly, information communication equipment, office electronic equipment and the like can be downsized.
Problems to be Solved by the Invention
The aforementioned conventional semiconductor device has, however, the following problems:
First, in the conventional semiconductor device, it is necessary to previously fabricate the wiring circuit sheet
102
, which increases the number of manufacturing processes. Also, the wiring circuit sheet
102
itself is expensive. Moreover, in order to adhere the wiring circuit sheet
102
onto the semiconductor chip
101
with the low elasticity material
103
sandwiched therebetween, it is necessary to provide a high performance placement machine, which increases the equipment cost. As a result, the manufacturing cost for the semiconductor device is increased as a whole.
Secondly, in connecting the element electrode
105
with the partial lead
104
extending from the wiring circuit sheet
102
, in particular when a fine line is used for the connection, the width and the thickness of the partial lead
104
are decreased, and hence the shape of the partial lead
104
becomes unstable, resulting in making the connection with the element electrode
105
difficult. Accordingly, the manufacturing cost is increased as well as the reliability of the connection is poor.
Thirdly, owing to this structure, such a semiconductor device cannot be manufactured until the semiconductor chip
101
is cut off from a wafer. Therefore, the semiconductor device is poor in rapidness in the manufacture, and cannot be tested in the state of a wafer. This is a serious obstacle to reduction of the manufacturing cost of the semiconductor device.
The present invention was devised to overcome the aforementioned conventional problems, and the object is providing a semiconductor device with high reliability, high packaging density and low cost that can be fabricated at wafer level up to a state close to the ultimate step of the manufacture, and a method for manufacturing the semiconductor device.
DISCLOSURE OF THE INVENTION
In order to achieve the aforementioned object, the following semiconductor device and method for manufacturing a semiconductor device are herein disclosed.
The basic semiconductor device of this invention comprises a semiconductor substrate including semiconductor elements; element electrodes arranged on a main surface of the semiconductor substrate and electrically connected with the semiconductor elements; an elastic material layer formed on the main surface of the semiconductor substrate from an insulating elastic material; an opening formed by partially removing the elastic material layer for exposing at least the element electrodes on the semiconductor substrate; a metal wiring layer continuously formed to stretch from the element electrodes over the elastic material layer; and external electrodes formed as a part of the metal wiring layer on the elastic material layer for electrical connection with external equipment.
In this manner, the external electrodes of the metal wiring layer are formed on the elastic material layer. Therefore, in mounting the semiconductor device on a mother board, stress applied to a connection part due to a difference in the coefficient of thermal expansion between the mother board and the semiconductor device can be absorbed by the elasticity of the elastic material layer. Thus, a semiconductor device having an improved function to relax stress can be realized.
Furthermore, since the metal wiring layer connected with the element electrodes is integrated with the external electrodes, the metal wiring layer can be formed by patterning a metal film deposited on the semiconductor substrate. Accordingly, there is no need to provide a wiring circuit sheet and equipment for the wiring circuit sheet as in the aforementioned conventional semiconductor device. Also in the manufacture, there is no need to conduct a process for connecting a partial lead with an element electrode through thermo bonding as in the procedures for the conventional semiconductor device. As a result, the manufacturing equipment and the number of manufacturing procedures can be reduced, and difficulty in the connection can be avoided. Thus, the manufacturing cost can be reduced.
In addition, the manufacturing procedures can be simplified because the metal wiring layer can be formed even when the semiconductor substrate is in the state of a wafer.
In the semiconductor device, the semiconductor substrate can be in the state of a wafer or in the s
Harada Yutaka
Kumakawa Takahiro
Murakami Shinji
Nakamura Yoshifumi
Sahara Ryuichi
Lee Eddie
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Robinson Eric J.
Warren Matthew E.
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