Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1999-03-15
2000-10-17
Beck, Shrive
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438722, 438738, 438742, 438770, 438721, H01L 21302
Patent
active
061331503
ABSTRACT:
A semiconductor device includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate, wherein the laminated film includes a semiconductor film, a metal film of refractory metal formed on the semiconductor film, a conductive oxidation preventing film disposed between the metal film and the semiconductor film, for preventing oxidation of the semiconductor film in an interface between the metal film and the semiconductor film, and an oxide film formed on a side surface of the semiconductor film and formed to extend into upper and lower portions of the semiconductor film in a bird's beak form.
REFERENCES:
patent: 5341016 (1994-08-01), Prall et al.
patent: 5573965 (1996-11-01), Chen et al.
patent: 5576579 (1996-11-01), Agnello et al.
patent: 5903053 (1999-05-01), Iijima et al.
patent: 5907188 (1999-05-01), Nakajima et al.
"Ti-Si-N Diffusion Barriers Between Silicon and Copper," J. S. Reid et al. IEEE Electron Device Letters, vol. 15, No. 8, Aug. 1994; p. 298-300.
"A Nitride-Isolated Molybdenum-Polysilicon Gate Electrode For MOS VLSI Circuits," Takashi Ito et al. IEEE Transactions On Electron Devices, vol. ED-33, No. 4, Apr. 1986; p. 464-468.
"Sputtered Ta-Si-N Diffusion Barriers In Cu Metallizations For Si," E. Kolawa et al. IEEE Electron Device Letters, vol. 12, No. 6, Jun. 1991; p. 321-323.
"An Inexpensive Diffusion Barrier Technology For Polycide Gate Electrodes With An SiN Layer Formed With ECR Nitrogen Plasma," Tetsuo Hosoya et al. Extended Abstracts Of The 1994 International Conference On Solid State Devices And Materials, Aug. 23, 1994; p. 422-424.
Extended Abstracts (The 41st Spring Meeting, 1994). The Japan Society Of Applied Physics And Related Societies, S. Suehiro et al.; p. 684.
Extended Abstracts The (41st Spring Meeting, 1994). The Japan Society Of Applied Physics And Related Societies, Y. Akasaka et al.; p. 684.
"Low-Resistivity Poly-Metal Gate Electrode Durable For High-Temperature Processing," Y. Akasaka et al. Proc. Of 12th VLSI Multilevel Interconnection Conference, Jun. 27-29, 1995; p. 168-174.
Poly-Metal Gate Process--Ultrathin WSiN Barrier Layer Impermeable To Oxidant In-Diffusion During Si Selective Oxidation, K. Nakajima et al.
"Morphology, and Thermal Stability of Me-Si-N (Me=Re, W, Ta) for Microelectronics"; Dutron et al.
Journal De Physique IV (Jun. 1995)', 5 (C5 Chemical Vapor Deposition, vol. 2), C5/1141-C5/1148.
Akasaka Yasushi
Miyano Kiyotaka
Nakajima Kazuaki
Suguro Kyoichi
Beck Shrive
Goudreau George
Kabushiki Kaisha Toshiba
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