Semiconductor device and method for manufacturing the same

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region

Reexamination Certificate

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C438S519000, C438S522000, C438S530000, C438S763000, C438S779000, C257S616000, C257S635000, C257S636000, C257S742000

Reexamination Certificate

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10998193

ABSTRACT:
A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020atoms/cm3is contained.

REFERENCES:
patent: 6624483 (2003-09-01), Kurata
patent: 2004/0070051 (2004-04-01), Sugiyama et al.
patent: 2004/0256639 (2004-12-01), Ouyang et al.
patent: 2005/0006637 (2005-01-01), Iinuma et al.
patent: 2005/0090066 (2005-04-01), Zhu et al.
patent: 2002-26318 (2002-01-01), None
Hwa Sung Rhee, et al., “A New Double-Layered Structure for Mass-Production-Worthy CMOSFETs with Poly-SiGe Gate”, 2002 Symposium On VLSI Technology Digest of Technical Papers, 2002, pp. 126-127.
S. Shimizu et al., “Gate Electrode Engineering by Control of Grain Growth for High Performance and High Reliable 0.18μm Dual Gate CMOS”, 1997 Symposium on VLSI Technology Digest of Technical Papers, 1997, pp. 107-108.

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