Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-02-02
2003-02-11
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S510000
Reexamination Certificate
active
06518633
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having an element isolation region and a method for manufacturing the same.
BACKGROUND
With the miniaturization of semiconductor devices (for example, MOS transistors) promoted in recent years, a further miniaturization of element isolation regions in semiconductor devices is required. In order to achieve a further miniaturization of element isolation regions in semiconductor devices, a trench isolation technique has been introduced. In the trench isolation technique, trenches are provided between semiconductor elements over a semiconductor substrate, and a dielectric material is filled in the trenches to isolate the semiconductor elements from one another. One example of the element isolation technique will be described below.
FIGS. 13 through 15
schematically show steps of forming element isolation regions using a conventional trench isolation technique.
FIG. 13
is a plan view of a semiconductor wafer over which a pad layer, a polishing stopper layer and a resist layer are successively deposited.
FIG. 13
also shows, for description purposes, a range of exposure of the resist layer formed over the semiconductor wafer.
FIGS. 14 and 15
schematically show cross-sectional views taken along a line B—B of
FIG. 13
in different steps.
First, a pad layer
112
, a polishing stopper layer
114
and a resist layer R
2
are successively deposited over a semiconductor wafer
110
. Then, as shown in
FIG. 13
, the resist layer R
2
only in a chip region
120
is exposed.
Next, as shown in FIG.
14
(
a
), the resist layer R
2
is developed to form the resist layer R
2
into a specified pattern. Then, the polishing stopper layer
114
and the pad layer
112
are removed using the resist layer R
2
as a mask.
Then, as shown in FIG.
14
(
b
), the resist layer R
2
is removed and then trenches
132
are formed in the semiconductor wafer
110
using the polishing stopper layer
114
as a mask.
Then, as shown in FIG.
15
(
a
), a dielectric layer
152
is formed over the semiconductor wafer
110
in a manner to fill the trenches
132
with the dielectric layer
152
.
Next, as shown in FIG.
15
(
b
), the dielectric layer
152
is polished by a chemical-mechanical polishing method (hereafter referred to as a “CMP method”). Through the steps described above, the dielectric layer
152
is embedded in the trenches
132
, and thereby trench isolation regions are formed.
In view of preventing the throughput of the exposure step from lowering, the resist layer R
2
in the non-chip region
122
is not generally exposed, as shown in FIG.
13
. As a result, as shown in FIG.
14
(
b
), after the trenches
132
are formed in the semiconductor wafer
110
, a relatively wide convex region
160
is formed in the non-chip region
122
adjacent to the chip region
120
. The relatively wide convex region
160
formed in the non-chip region
122
adjacent to the chip region
120
causes the following problems.
As shown in FIG.
15
(
a
), when the dielectric layer
152
is formed over the semiconductor wafer
110
, the dielectric layer
152
is thickly deposited over the wide convex region
160
. If the dielectric layer
152
is polished while the dielectric layer
152
is thickly deposited in the wide convex region
160
, the dielectric layer
152
deposited in the wide convex region
160
remains when the polishing of the dielectric layer
152
deposited over the chip region
120
is completed, as shown in FIG.
15
(
b
). Also, due to the presence of the thick dielectric layer
152
formed in the wide convex region
160
, the dielectric layer
152
remains in an area over a convex section
162
adjacent to the wide convex region
160
. In other word, the dielectric layer
152
in the chip region
120
remains in an area over the convex section
162
adjacent to the non-chip region
122
. When the dielectric layer
152
in the chip region
120
remains in an area over the convex section
162
adjacent to the non-chip region
122
, the polishing stopper layer
114
cannot be removed, and a element cannot be formed over the convex section
162
.
Furthermore, if the dielectric layer
152
is polished while the dielectric layer
152
is thickly deposited in the wide convex region
160
, thinning and dishing phenomenon occur. These phenomenon cause variations in the thickness of the dielectric layer
152
.
Because of the reasons described above, when the relatively wide convex region
160
is formed in the non-chip region
122
adjacent to the chip region
120
, chips that are formed in outermost areas (areas indicated by crosses (x) in
FIG. 13
) of the chip region
120
may become bad chips. In other words, the yield of chips formed in the chip region other than the outermost areas is lowered.
SUMMARY
It is an object of the present invention to provide semiconductor wafers, a method for processing the same and a method for manufacturing semiconductor devices, which improve the yield of chips formed in a chip region other than outermost areas of the chip region.
(1) In accordance with a first embodiment of the present invention, a method is provided for processing a semiconductor wafer having a chip region and a non-chip region. In accordance with the method, trench isolation regions are formed in the semiconductor wafer, and dummy trench isolation regions are formed in at least a part of the non-chip region of the semiconductor wafer, wherein the dummy trench isolation regions are formed in a region extending by a specified distance into the non-chip region from a boundary between the chip region and the non-chip region.
The “chip region” used here refers to a region in a semiconductor wafer where chips can be formed according to a given pattern, and the “non-chip region” used here refers to a region in the semiconductor wafer where chips cannot be formed according to the given pattern.
In the method for processing a semiconductor wafer in accordance with the first embodiment, dummy trench isolation regions are formed in at least a part of the non-chip region of the semiconductor wafer. In other words, when trenches are formed in the semiconductor wafer to form trench isolation regions in the semiconductor wafer, dummy trenches are formed in the non-chip region. As a result, when a dielectric layer is filled in the trenches, the dielectric layer is prevented from being thickly deposited in a convex region in the non-chip region. Therefore, after the dielectric layer is polished, the dielectric layer is prevented from remaining in convex sections in the chip region adjacent to the non-chip region by the influence of the dielectric layer deposited over the non-chip region. As a result, the yield of chips to be formed in the chip region adjacent to the non-chip region is increased.
The specified distance may preferably be 1.5 mm or greater. When the specified distance is 1.5 mm or greater, the dielectric layer is prevented from remaining over convex sections in the chip region adjacent to the non-chip region.
More preferably, the specified distance may be between 2 mm and 5 mm. When the specified distance is 2 mm or greater, the dielectric layer can be more securely prevented from remaining over convex sections in the chip region adjacent to the non-chip region. Also, when the specified distance is 5 mm or smaller, the chip region can be more effectively defined over the semiconductor wafer.
(2) In accordance with a second embodiment of the present invention, a method is provided for processing a semiconductor wafer having a chip region and a non-chip region. In accordance with the method, the method comprises step (A) of forming trench isolation regions in the semiconductor wafer, wherein step (A) comprises the steps of:
(a) forming a polishing stopper layer having a specified pattern over the semiconductor wafer;
(b) forming trenches in the chip region and dummy trenches in at least a portion of the non-chip region in the semiconductor wafer using at
Kojima Kenji
Mori Katsumi
Harness & Dickey & Pierce P.L.C.
Nelms David
Nhu David
Seiko Epson Corporation
LandOfFree
Semiconductor device and method for manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3136948