Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Reexamination Certificate
2001-08-02
2002-12-17
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
C438S444000, C438S452000
Reexamination Certificate
active
06495431
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device in which an element isolating region is formed using LOCOS (LOCal Oxidation of Silicon) and a method for manufacturing the same.
The present application claims priority of Japanese Patent Application No.2000-236213 filed on Aug. 3, 2000, which is hereby incorporated by reference.
2. Description of the Related Art
An LSI (Large Scale Integration) known as a representative of semiconductor devices includes desired circuit devices formed in each of a plurality of element regions which is dielectrically isolated from each other by an element isolating region on a semiconductor substrate. This element isolating region has conventionally been formed using LOCOS.
FIGS. 5A
to
5
C are flow diagrams for schematically showing an element isolating region forming method utilizing a LOCOS method.
As shown in
FIG. 5A
, first a silicon oxide (SiO
2
) film
52
is formed as a pad insulating film by thermal oxidation and then a silicon nitride (SiN) film
53
is formed as an oxidation preventing film by CVD (Chemical Vapor Deposition) on a silicon substrate
51
. In this configuration, oxidation preventing film, silicon oxide film
52
, is used as a buffer film to prevent a crystal defect from occurring in a surface of the silicon substrate
51
if the silicon nitride film
53
is formed directly formed on the silicon substrate
51
. Next, by photolithography, the silicon nitride film
53
is selectively etched away only in an element-isolating region formation-expected region
54
on the silicon substrate
51
to thereby expose the silicon oxide film
52
.
Next, as shown in
FIG. 5B
, by performing thermal oxidation (field oxidation) on the silicon substrate
51
in an oxidizing atmosphere, a field silicon oxide film (field oxide film
55
) is formed at such a position in the element-isolating region formation-expected region
54
that is not masked by the silicon nitride film
53
. As a result, an element isolating region is formed which is made up of the field oxide film
55
. Also, the field oxide film
55
has a so-called bird's beak
55
A formed at its sides. Next, as shown in
FIG. 5C
, by removing the silicon nitride film
53
and the silicon oxide film
52
, the silicon substrate
51
has, formed thereon, a plurality of element regions
56
which is dielectrically isolated from each other by the element isolating region made up of the field oxide film
55
.
Afterwards, thus obtained silicon substrate
51
undergoes repeatedly such required process steps as impurity introduction and etching, so that desired circuit elements are formed in the element regions
56
, thus completing a semiconductor device.
As mentioned above, the field oxide film
55
formed by LOCOS has the bird's beak
55
A at its sides, which bird's beak
55
A bites into the element region
56
. Since a depth by which the bird's beak
55
A bites into the element region
56
is roughly proportional to film thickness of the field oxide film
55
, if the field oxide film
55
is formed thick to increase isolation dielectric strength of a circuit element formed in the element region
56
, bite-in depth of the bird's beak
55
A is also increased. As a result, a lateral dimension L of the element region
56
is decreased and will be more and more restricted as the LSIs will be demanded to have an even higher integration density in the future, thus leading to a major problem.
If the field oxide film
55
is formed thin to decrease the bite depth of the bird's beak
55
A, on the other hand, the isolation dielectric strength is also decreased, thus finding difficulty in application to such a circuit element that requires a higher isolation dielectric strength. Thus, with the conventional element isolating region forming method using a LOCOS step only once, the bird's beak
55
A cannot avoid biting deeply into the element region
56
particularly, when the element isolating region is formed rather thick.
Also, as the bird's beak
55
A bites into the element region
56
deeper, it becomes more difficult to flatten the surface of the element region
56
, so that when a MOS (Metal Oxide Semiconductor) transistor is formed as the circuit element in the element region
56
, a channel region is not flattened in shape, thus resulting in fluctuations in effective lateral dimension L, hence in transistor characteristics.
It should be noted that such a semiconductor LSI device including a flash memory, for example, is widely used in information equipment or a like that includes a first type of circuit element that requires a higher isolation dielectric strength (supply voltage: 15-18V) like a memory transistor and a second type of circuit element that requires only a lower isolation dielectric strength (supply voltage: 2.5-3.3V) like a logic transistor in a peripheral circuit which are mixed on the same substrate. In such a configuration, the first type of circuit element requires a thicker element isolating region and the second type of circuit element, only a thinner one.
In manufacturing of such a semiconductor device, however, performing the LOCOS step only once is not sufficient to form an element isolating region that meets requirements of both types of circuit elements described above.
In view of the above, such a semiconductor device manufacturing method has conventionally been provided that forms an element isolating region by performing the LOCOS processing in two steps. The following will describe this semiconductor device manufacturing method along its steps with reference to
FIGS. 6A
to
6
H. Description is made with reference to the above-mentioned example where the first type of circuit element requiring a thicker element isolating region and the second type of circuit element requiring only a thinner element isolating region are formed in a mixed manner on the same substrate.
First, as shown in
FIG. 6A
, on a silicon substrate
61
is formed by thermal oxidation, a silicon oxide film
62
as the pad insulating film with a film thickness of 18-22 nm, on which is then formed by CVD a silicon nitride film
63
as the oxidation preventing film with a film thickness of 130-170 nm. And, on the silicon substrate
61
are defined a first element-isolating region formation-expected region
64
A for a first circuit element requiring a thicker element isolating region and a second element-isolating region formation-expected region
64
B for a second circuit element requiring only a thinner element isolating region.
Next, as shown in
FIG. 6B
, a photo-resist is applied by photolithography everywhere on the silicon substrate
61
, which is then exposed and developed to form a photo-resist (PR) film
66
having such a pattern that has an opening
66
A therein with a width dimension of 700-750 nm only on the above-mentioned first element-isolating region formation-expected region
64
A. Next, as shown in
FIG. 6C
, the silicon nitride film
63
and the silicon oxide film
62
which are exposed are sequentially and selectively dry-etched and patterned using the photo-resist film
66
as a mask to thereby form an opening
67
with roughly a same dimension as the opening
66
A, thus exposing the silicon substrate
61
. Subsequently, the silicon substrate
61
is selectively dry-etched on its surface to thereby form a recess
68
with roughly a same width dimension of 700-750 nm as the opening
67
and a depth of 70-80 nm. Next, the photo-resist film
66
is removed.
Next, as shown in
FIG. 6D
, the silicon substrate
61
is heat treated, as exposed in an oxidizing atmosphere, at 1000-1100° C. for 20-30 minutes as first field oxidation (thermal oxidation). This permits the silicon nitride film
63
having the opening
67
therein to be used as a mask to thereby form a first field oxide film
69
having a film thickness of 270-350 nm and a width of 1.0-1.3 &mgr;m constituting part of the first element isolating region on the surface of the silicon substrate
61
in which the recess
68
of the fir
McGinn & Gibb PLLC
NEC Corporation
Niebling John F.
Pompey Ron
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