Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2000-06-22
2001-12-25
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C257S197000
Reexamination Certificate
active
06333236
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transistor having a hetero-junction, and more particularly to a semiconductor device that enables the achievement of a base having the desired resistance and good repeatability, and to a method for manufacturing such a semiconductor device.
2. Related Art
A method for manufacturing a bipolar transistor having an AlGaAs or GaAs hetero junction in the prior art is described with reference made to FIG.
5
and FIG.
6
.
On a GaAs substrate
101
a first n-type GaAs layer
102
of 500 nm thickness, a second n-type GaAs layer
103
of 500 nm thickness, a p-type GaAs layer
104
of 50 nm thickness, an n-type Al
0.2
Ga
0.8
As layer
106
of 30 nm thickness, and a third n-type GaAs layer
107
of 20 nm thickness are sequentially grown, using an MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy) process. The doping of each layer is made so as to enable functioning as a device. Next, a photolithographic process is used to form a photoresist layer
108
having a dimension of approximately 0.8 &mgr;m thickness (FIG.
5
(
a
)).
Next, using a gas mixture of, for example, SF
6
and BC
1
3
, selective dry etching is done so as to etch the third GaAs layer
107
, thereby forming an n-type GaAs emitter contact layer
127
. When this is done, etching is stopped at the surface of the n-type Al
0.2
Ga
0.8
As layer
106
(FIG.
5
(
b
))
Next, sulfuric acid and hydrogen peroxide or the like are used to perform wet etching of the n-type Al
0.2
Ga
0.8
As layer
106
, and expose the surface of the p-type GaAs layer
104
(FIG.
6
(
a
)). When this is done, an etching rate of the n-type Al
0.2
Ga
0.8
As layer
106
is equal to that of the p-type GaAs layer
104
, so that the amount of etching of the n-type Al
0.2
Ga
0.8
As layer
106
is controlled by the etching time, and part of the p-type GaAs layer
104
is etched in the process. Additionally, because this is anisotropic etching, variations occur in the emitter dimensions.
In the case in which the above-noted etching shown in FIG.
5
(
b
) and FIG.
6
(
a
), the overall etching time becomes long, and fine control of the emitter dimensions becomes difficult. Therefore, there is a need to perform separate etching of the n-type Al
0.2
Ga
0.8
As layer
106
and the p-type GaAs layer
104
and, thereby causing an increase in the number of process steps.
Finally, an n-type GaAs sub-collector layer
122
, an n-type GaAs collector layer
123
, a p-type GaAs base layer
124
, an emitter electrode
129
, a base electrode
130
, and a collector electrode
131
are formed using conventional processes, thereby fabricating the transistor (FIG.
6
(
b
)).
The second prior art example shown in
FIG. 7
is a transistor that is disclosed in the Japanese Examined Patent Publication (KOKOKU) No.6-12778.
In the hetero-bipolar transistor shown in
FIG. 7
, an n
− −
type GaAs collector layer
223
with a donor concentration of 1×10
16
atoms/cm
3
, a p
−
type GaAs base layer
224
with an acceptor concentration of 1×10
18
atoms/cm
3
, an undoped Al
0.4
Ga
0.6
As emitter barrier layer
225
of thickness 10 nm, and an n
−
type Al
0.2
Ga
0.8
As emitter layer
226
with a donor concentration of 5×10
17
atoms/cm
3
are formed onto an n
+ −
type GaAs substrate
201
having a donor concentration of 1×10
18
atoms/cm
3
. In this drawing, the reference numeral
231
denotes a collector electrode, the reference numeral
230
is a base electrode, and the reference numeral
229
is an emitter electrode.
In this prior art example, carriers which are injected into the base layer
224
from the emitter layer
226
, passing through the emitter barrier
225
, are accelerated by the band discontinuity between the emitter barrier
225
and the base layer
224
, so as to pass through the base layer
224
at a high speed, thereby enabling ultra-highspeed operation.
As described above, in the first prior art example, when removing the emitter layer, the base layer is also etched. Therefore, there is an increase in the resistance of the base region and the occurrence of variations of the base resistance. Additionally, because it is difficult to control emitter dimension, there is the added problem of the occurrence of variations of the emitter current value.
In the second prior art example as shown in
FIG. 7
, a thin undoped Al
0.4
Ga
0.6
As emitter barrier layer
225
is sandwiched between an Al
0.2
Ga
0.8
As emitter layer
226
and a GaAs base layer
224
, however, it is impossible to use an undoped Al
0.4
Ga
0.6
As emitter barrier layer
225
as an etching stopper, therefore, it is impossible to achieve selective etching of the Al
0.2
Ga
0.8
As emitter layer
226
with respect to the undoped Al
0.4
Ga
0.6
As emitter barrier layer
225
. Thus, this structure has the same drawback as that of the first prior art example.
Accordingly, it is an object of the present invention to provide a bipolar transistor having a hetero-junction, in which patterning of an emitter layer does not affect the dimension of the base layer therebelow, thereby preventing an increase in the resistance of the base layer, and also in which dimensional control of the emitter is facilitated. It is a further object of the present invention to provide a method for manufacturing the above-noted semiconductor device.
SUMMARY OF THE INVENTION
In order to achieve the above-noted objects, the present invention has the following technical constitution.
Specially, the first aspect of the present invention is a hetero-junction bipolar transistor comprising, an n-type GaAs sub-collector layer formed on a semi-insulating GaAs substrate, an n-type GaAs collector layer formed on the n-type GaAs sub-collector layer, a p-type base layer formed on the n-type GaAs collector layer, an undoped Al
x
Ga
1−x
As stopper layer formed on the p-type base layer, an n-type Al
Y
Ga
1−Y
YAs emitter layer formed on the undoped Al
X
Ga
l−X
As stopper layer, and an n-type GaAs emitter contact layer formed on the n-type Al
Y
Ga
1−Y
As emitter layer, wherein the value Y in said n-type Al
Y
Ga
1−Y
As emitter layer is 0 to 0.4, and the value X in said undoped Al
X
Ga
1−X
As stopper layer is 0.7 to 1.0.
In the second aspect of the present invention, the n-type GaAs emitter contact layer is replaced with In
Z
Ga
1−Z
As having a value Z of 0 to 0.5.
The third aspect of the present invention is a method for fabricating a hetero-junction bipolar transistor comprising the steps of: a first step of forming an n-type GaAs sub-collector layer, an n-type GaAs collector layer, a p-type GaAs base layer, an undoped Al
X
Ga
1−X
As stopper layer with a value X of 0.7 to 1.0, an n-type Al
Y
Ga
1−Y
As emitter layer with a value Y of 0 to 0.4, an n-type GaAs emitter contact layer on a semi-insulating GaAs substrate in this sequence; a second step of forming a resist layer on the n-type GaAs emitter contact layer and patterning the resist layer; a third step of etching the n-type GaAs emitter contact layer and the n-type Al
Y
Ga
1−Y
As emitter layer using the resist layer and a first etching fluid with the undoped Al
X
Ga
1−X
As stopper layer as an etching stopper, so as to form an n-type GaAs emitter contact and an n-type Al
Y
Ga
1−Y
As emitter, and expose a surface of the undoped Al
X
Ga
1−X
As stopper layer; and a fourth step of removing the exposed undoped Al
X
Ga
1−X
As stopper layer so as to expose a surface of the p-type GaAs base layer using a second etching fluid.
In the fourth aspect of the present invention, the first etching fluid is a mixture of a citric acid aqueous solution and hydrogen peroxide aqueous solution, and when a concentration of the hydrogen peroxide aqueous solution is 28 to 32 percent by weight, and a concentration of the citric acid aqueous solution is 20 to 50 percent by weight, the mixture ratio of the citric acid aqueous solution for the hydrogen peroxide aqueous solution
Chaudhuri Olik
McGinn & Gibb PLLC
NEC Corporation
Wille Douglas A.
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