Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-12-13
2002-02-05
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S763000, C257S764000, C257S770000
Reexamination Certificate
active
06344694
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, more in detail to the semiconductor device having an interconnect, including an electrode, made of a titanium silicide film or a titanium polycide film (a composite film including a polysilicon film and a titanium silicide film formed thereon), and the method for manufacturing the same.
(b) Description of the Related Art
With the progress of miniaturization of a semiconductor device in recent years, interconnects in the semiconductor device are required to have reduced resistances. The interconnects are also required to have a resistance to heat in order to be stabilized against a thermal treatment during manufacture. In recent years, a tungsten silicide film and a tungsten polycide film (a composite film including a polysilicon film and a tungsten silicide film formed thereon) have been employed as an interconnect material having the desired resistance to heat.
A conventional MOS transistor employing the tungsten silicide film as an interconnect material and a method for manufacturing the same will be briefly described referring to
FIGS. 1A
to
1
C which are a series of vertical sectional views sequentially showing manufacture of a gate interconnect and an electrode connected thereto in a conventional semiconductor device.
After an oxide film
302
for separating elements is selectively formed on the surface of a silicon substrate
301
followed by formation of a gate dielectric film
303
, a polysilicon film
304
for a gate interconnect of N-type conductivity having a thickness of 60 nm or more is formed. Phosphorous, for example, used as N-type impurities is doped into the polysilicon film
304
during the formation thereof by means of a chemical vapor-phase deposition (CVD) method. After an undoped polysilicon film is formed, a thermal treatment in an oxidative ambient including POCl
3
for thermal diffusion or ion injection of the phosphorous may be conducted for implementing the doping.
Then, a spontaneous oxidation film, if any, on the polysilicon film
304
is removed with a solution containing hydrofluoric acid. A tungsten silicide film
305
having a thickness of 100 nm or more is deposited on the polysilicon film
304
for forming a polycide structure. The tungsten silicide film
305
may be formed by employing the CVD method or a physical vapor-phase deposition (PVD) method such as sputtering.
Phosphorous is then injected into the tungsten silicide film
305
.
Thereafter, a silicon nitride film
306
having a thickness of 100 nm or more is formed on the tungsten silicide film
305
(FIG.
1
A).
By using ordinary resist application, exposure and development steps, a resist film (not shown) is patterned to have a gate electrode shape by anisotropic dry etching.
After the removal of the resist film, impurity ions are injected into the exposed silicon substrate
301
for forming an LLD (Lightly Doped Drain) region or an extension region, if necessary.
Then, a dielectric film (not shown) which properly covers steps in the wafer is formed by means of the CVD method. Side walls
308
made of dielectric films are formed by anisotropic etching-back. By employing, as a mask, the side walls
308
and the gate electrode formed by the films
304
to
306
on the silicon substrate
301
, impurity ions are injected into the silicon substrate
301
. A successive thermal treatment at an activation temperature between 800 and 900° C. forms a diffused layer
309
(FIG.
1
B).
After an interlayer dielectric film
310
is formed, a via hole
311
reaching to the tungsten silicide film
305
is formed in the interlayer dielectric film
310
.
Then, a polysilicon film
312
which properly covers steps in the wafer is deposited by means of the CVD method. The polysilicon
312
on the interlayer dielectric film
310
is removed by etching-back leaving the polysilicon
312
in the via hole
311
. Phosphorous is injected into the polysilicon
312
remaining in the via hole
311
.
After a tungsten silicide film
313
is deposited on the interlayer dielectric film
310
, the tungsten silicide film
313
is patterned to a desired interconnect shape by means of anisotropic dry etching by using resist application, exposure and development steps (FIG.
1
C).
Thereafter, the injected impurities are activated for forming, for example, a DRAM (Dynamic Random Access Memory). The activation also serves as a capacitance film forming step and a reflow and sintering step for the interlayer dielectric film.
The technique for injecting the phosphorous into the tungsten silicide film
305
in the above manufacturing steps is described, for example, in JP-A-2(1990)-292866. The phosphorous injection conducted for providing the excessive phosphorous in the tungsten silicide film
305
before the thermal treatment suppresses depletion of the polysilicon and increase of the plug resistance.
In the gate electrode including the tungsten silicide
305
on the polysilicon
304
doped with the N-type impurities such as phosphorous, the phosphorous may diffuse from the polysilicon
304
into the silicide
305
to deplete the polysilicon
304
on the gate dielectric film
303
.
When an electric connection is formed on the tungsten silicide
305
by employing the polysilicon plug
312
doped with the phosphorous, the phosphorous may also diffuse from the polysilicon
312
into the tungsten silicide to increase the entire resistance of the plug.
The excessive phosphorous injection into the tungsten silicide film
305
in advance prevents the phosphorous diffusion from the adjacent polysilicons
304
and
312
during the thermal treatment. The prevention of the decrease of the phosphorous in the polysilicons
304
and
312
suppresses the depletion and the increase of the plug resistance.
However, in order to realize a DRAM having integration larger than 1 G-bit, an interconnect width should be narrowed while maintaining the sensibility of a sense amplifier. Employment of the tungsten silicide film as an interconnect material requires the film thickness entirely thicker than the gate interconnect width for maintaining the low resistance. In other words, a large aspect ratio is needed to cause a problem that formation of the gate structure including the tungsten silicide film is difficult.
In order to realize the DRAM having 1 G-bit or more, for example, a sheet resistance is desirably maintained at 5 &OHgr;/□ or less. However, the realization of the sheet resistance of 5 &OHgr;/□ or less by employing the tungsten silicide film having a resistivity of about 100 &mgr;&OHgr; cm requires the tungsten silicide film having a thickness of 200 nm.
The thickness of an interconnect made of the tungsten silicide film immediately after the addition to the gate electrode amounts to 360 nm or more including the underlying polysilicon layer of 60 nm or more and the overlying nitride layer of 100 nm or more. The above thickness is twice or more the gate interconnect width of 180 nm of the DRAM having around 1 G-bit.
The larger aspect ratio makes it difficult to form a via hole in a diffused layer between gate electrodes and to embed a contact electrode in a DRAM cell.
A titanium silicide film having low resistivity between 20 and 25 &mgr; &OHgr; cm may be employed for thinning the interconnect in place of the tungsten silicide film having the higher resistance.
The employment of the titanium silicide film causes another problem that a larger precipitate is generated in the film. The larger precipitate is a crystal of which main components are titanium (Ti) and phosphorous (P), and may grow to a size which can be observed through the overlying dielectric film with an optical microscope.
FIG. 2
is a microphotograph showing an image of the larger precipitate taken with a scanning electron microscope (SEM). The SEM image is obtained by observing the larger precipitate remaining on the polysilicon with the SEM after removal of the overlying dielectric film and the titanium si
Clark Jhihan B
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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