Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-10
2003-12-30
Thompson, Craig (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000
Reexamination Certificate
active
06670673
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based on and incorporates herein by reference Japanese Patent Application No. 2001-120163 filed on Apr. 18, 2001.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having an insulated gate. The present invention is applicable to a power MOSFET (Metal-Oxide-Silicon Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or a thyristor.
A power MOSFET having low ON-resistance was previously proposed by the present inventor. As shown in
FIG. 14
, the power MOSFET is has an n
+
-type substrate J
1
making up an n
+
-type drain region and, an n
−
-type drift region J
5
, a p-type base layer J
4
, an n
+
-type source layer J
3
, and a plurality of gate electrodes J
2
. The gate electrodes J
2
are plate-like and are embedded upright in the power MOSFET to divide the p-type base layer J
4
and the n
+
-type source layer J
3
into a plurality of p-type base regions J
4
and a plurality of n
+
-type source regions J
3
, respectively. With this structure, channels are formed to extend in the lateral direction of FIG.
14
.
The power MOSFET shows especially low ON resistance in the range between low and medium breakdown voltage. For example, when each gate electrode J
2
has a depth of 30 micrometers, the power MOSFET has a correlation shown in
FIG. 15
between normalized ON resistance and breakdown voltage. The power MOSFET has a lower normalized ON resistance than the theoretical limit of a vertical DMOS (double-diffused MOS) in the breakdown voltage range between about 40 and 300 V.
The power MOSFET described above is manufactured in the manner shown in
FIGS. 16A
to
16
E. As shown in
FIG. 16A
, a silicon oxide film J
6
formed on a surface of the substrate J
1
is defined using photolithography. The substrate J
1
, when masked by the defined film J
6
, is etched to form a trench J
7
, as shown in FIG.
16
B. The trench J
7
is filled with the n
−
-type drift region J
5
, the p-type base layer J
4
, and the n
+
-type source layer J
3
in this order using an epitaxial growth technique, as shown in
FIGS. 16C and 16D
. Afterward, the three layers above the level of the silicon oxide film J
6
are removed. Although not illustrated, the power MOSFET is completed with the following steps or steps similar to the following steps. A plurality of trenches are formed to divide the p-type base layer J
4
and the n
+
-type source layer J
3
into a plurality of n
+
-type source regions J
3
and a plurality of p-type base regions J
4
, respectively. A gate oxide layer is formed on the surface defining each trench. Then, each trench is filled with the gate electrode J
2
.
After the trench J
7
is filled with the layer J
3
, a crystalline defect or void tends to occur in the trench J
7
because the surface of the layer J
3
grows inwardly from the sidewall of the trench J
7
and joins, or meets itself, in the trench J
7
. If the crystalline defect or void is generated in the proximity of the gate oxide layer, the breakdown voltage of the gate is reduced.
FIG. 17
shows a structural modification, in which each gate electrode J
2
is divided in two and the n
+
-type source layer J
3
is widened. This modification prevents the breakdown voltage from being reduced by the crystalline defect. However, this modification enlarges the size of the device and decreases the area of the channel. The normalized ON resistance increases due to the decreased area of the channel.
In addition, the p-type base layer J
4
is formed in the lightly-doped n
−
-type drift region J
5
in the proposed power MOSFET, so the electric field is unfavorably concentrated at the bottom corner of the layer J
4
, as shown in
FIG. 18
, which is a simulation of electric field distribution when 80 V is applied to the drain.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems with an object to prevent the breakdown voltage from being reduced without increasing the ON resistance and with another object to suppress the electric field concentration at the bottom corner of the layer J
4
.
In the present invention, a power MOSFET is fabricated from an n
+
-type substrate having a top surface and a back surface, which is opposite to the top surface. A first trench is formed in the substrate at a predetermined depth from the top surface. A p-type base region is formed in the first trench. An n
−
-type drift region is formed in the p-type base region. An n
+
-type drain region is formed in the n
−
-type drift region. A second trenche is formed to pass through the p-type base region in a lateral direction. A gate insulating film is formed on a surface defining the second trench. A gate electrode is formed on each gate insulating film to fill the second trench.
The n
+
-type drain region has a location where opposed parts of an epitaxial growth layer meet, thus the gate electrode does not need to be positioned to avoid this location. Therefore, the breakdown voltage is maintained without increasing the ON resistance. In addition, the n
−
-type drift region is formed in the p-type base region, so the electric field concentration at the bottom corner of the p-type base region is reduced.
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patent: 5438215 (1995-08-01), Tihanyi
patent: 5723891 (1998-03-01), Malhi
patent: 5828101 (1998-10-01), Endo
patent: 6281547 (2001-08-01), So et al.
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U.S. patent application Ser. No. 09/688,154, Yamaguchi et al., filed Oct. 16, 2000.
Denso Corporation
Rosz & Bethards, PLC
Thompson Craig
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