Semiconductor device and method for making the same

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357 65, 357 71, H01L 2348, H01L 2944, H01L 2954, H01L 2962

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048841200

ABSTRACT:
An improved interconnection structure and method for forming the interconnection in a semiconductor device having multilayered interconnection structure in which a contact hole for electrically connecting a first layer interconnection to a predetermined region of a semiconductor substrate and a through hole for electrically connecting a second layer interconnection to the first layer interconnection are formed in the regions overlapping with each other in planer layout. In the interconnection structure of the present invention, hillocks effective to compensate for the contact hole step are formed in the first layer interconnection only in the region of the contact hole of the first layer interconnection. In the method for forming the interconnection according to the present invention, a first layer interconnection is formed and a chemical conversion process is selectively performed to form a film which is more rigid than the first layer interconnection film on a predetermined region of the first layer interconnection film, and then a heat process is performed to generate hillocks only at the region of the contact hole of the first layer interconnection film. The second layer interconnection film is formed thereafter.

REFERENCES:
patent: 3866311 (1975-02-01), Salles et al.
patent: 4698125 (1987-10-01), Rhodes
patent: 4707457 (1987-11-01), Erb
patent: 4734754 (1988-03-01), Nikawa
"Patents Abstracts of Japan", vol. 10, no. 54 (mar. 4, 1986).
Cadien and Losee, "A Method for Eliminating Hillocks in Integrated-Circuit Metallizations", J. Vac. Sci. Tecnol. B2(1), (jan.-Mar. 1984) pp. 82-83.
D. Culver et al., "Modeling of Metal Step Coverage for Minimum Feature Size Contacts and Vias", IEEE 1985 V-MIC Conference CH 219-2185/0000-03994, 01.00, pp. 399-407.

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