Semiconductor device and method for making the same

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation

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438691, H01L 2176

Patent

active

056331908

ABSTRACT:
Disclosed is a semiconductor device in which dummy regions which are lower than an isolated element region are formed around the isolated element region. Another dummy region which has a height nearly equal to those of element regions may be formed at a non-element-region-existing region, accompanying with lower dummy regions. The method for making the semiconductor device has the steps of suitably forming the element regions and dummy regions on a insulating layer on a substrate, depositing a insulator on the entire surface of the insulating layer and polishing the insulator to obtain a plane surface.

REFERENCES:
patent: 4378630 (1983-04-01), Horng et al.
patent: 5120675 (1992-06-01), Pollack
H. Nishizawa et al., "Fully SiO.sub.2 Isolated High Speed Self-Aligned Bipolar Transistor on Thin SOI", 1991 Symposium on VLSI Technology, Digest of Technical Papers, pp. 51-52.

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