Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-27
2003-08-26
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S410000, C257S411000, C257S327000, C438S216000, C438S261000
Reexamination Certificate
active
06611031
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a semiconductor device and method for its manufacture, and more specifically to a semiconductor device including an insulated gate field effect transistor (IGFET) having a particular gate electrode insulation structure and a method of its manufacture.
BACKGROUND OF THE INVENTION
In order to reduce manufacturing costs and provide more components on a semiconductor device, semiconductor devices are being made with finer structures. Such components include insulated gate field effect transistors (IGFETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs). Semiconductor devices such as memory devices and logic devices are now being made in which minimum line widths are about 0.15 &mgr;m.
As IGFETs become finer, the film thickness of the gate insulating film becomes finer. In such cases, the gate insulating film can be a silicon oxide film having a thickness of about several nanometers. In a conventional IGFET, such as a MOSFET structure, once the gate insulating film is made thinner, a steep band bending may occur on the surface of a drain region that is overlapped by and separated from the gate electrode by the gate insulating film. Although in this case, while the gate electrode may be biased so that the MOSFET is in the non-conduction state, a leakage current may be increased due to inter-band tunneling of electrons between a valence band and a conduction band. The tunneling occurring due to the above-mentioned band bending has been reported in “International Electron Device Meeting (IEDM), 1987, pp. 718-721.”
The above-mentioned tunneling phenomenon will now be described with reference to
FIGS. 1A and 1B
.
Referring now to
FIG. 1A
, a cross sectional view of a portion of a conventional N-channel MOSFET is set forth.
As illustrated in
FIG. 1A
, a silicon substrate having a P-type conductivity is connected to a ground potential. The potential Vg of a gate electrode is also connected to the ground potential. The gate electrode is separated from the substrate by a gate insulating film. A drain region having a n
+
type conductivity is formed on the substrate surface. An electric potential Vd is applied to the drain region. Once the electric potential Vd is applied to the drain region, a depletion region (indicated by the dashed line) is formed at the p-n junction formed at the interface of the drain region and substrate. Holes and electrons may be produced in the depletion region. The electric field causes the positive holes to flow into the substrate and the negative electrons to flow into the drain region. In this way, a leakage current is caused by inter-band tunneling as mentioned above.
Referring now to
FIG. 1B
, a band diagram of an N-channel MOSFET and a P-channel MOSFET is set forth. The band diagram on the left illustrates a band diagram of an N-channel MOSFET as shown in
FIG. 1A
along the line X-Y. The band diagram on the right illustrates a band diagram along a similar line for a P-channel MOSFET.
In the case of the N-channel MOSFET, the band has a higher energy at the gate (G) and the energy is lowered across the gate insulating film (Ox) to the drain (D). As the gate insulating film (Ox) becomes thinner, a steep band bending occurs in the drain (D). Thus, electrons in the valence band may tunnel to the conduction band thereby forming holes in the valance band. This activity of the electrons flowing from the substrate to the drain and creating holes flowing to the substrate create a leakage current in the substrate.
In the case of the P-channel MOSFET, the band energy levels are reversed. Thus, the band has a lower energy at the gate (G) and the energy is increased across the gate insulating film (Ox) to the drain (D). As the gate insulating film (Ox) becomes thinner, a steep band bending occurs in the drain (D). Thus, electrons in the valence band may tunnel to the conduction band thereby forming holes in the valance band. This activity of the electrons flowing from the drain to the substrate and creating holes flowing to the drain create a leakage current in the substrate.
Japanese Laid-Open Patent Publication No. Hei 1-264264 (JP 1-264264) discloses a method for preventing such a leakage current due to inter-band tunneling. In JP 1-264264, inter-band tunneling is prevented by moderating the bending by altering a material to change the work function of the gate electrode in a region which overlaps the drain region. In this method, the gate electrode is constructed with conductor materials of different conductivity types in which the first conductivity type is used for the gate electrode over the channel area of the transistor and the second conductivity type is used for the gate electrode over the source-drain regions of the transistor. The conductor materials of different types are chosen such that their work functions are different from each other.
The present inventor has investigated, in detail, the leakage current caused by the above-mentioned inter-band tunneling in a semiconductor device using 256 Megabit and a 1 Gigabit Dynamic Random Access Memory technology.
The investigations have indicated that there appears to be a large influence in the leakage current caused by the above-mentioned inter-band tunneling. The influence of the leakage current is likely to appear when the drain voltage becomes relatively high, as in a voltage boosting circuit. In such a boosting circuit the inter-band tunneling phenomenon is typically found in P-channel MOSFETs instead of N-channel MOSFETs. Thus, in semiconductor devices there are transistors where inter-band tunneling may be problematic, but other transistors where inter-band tunneling may not occur. The present inventor has found that state of the art semiconductor devices may require a technique to optionally suppress inter-band tunneling depending upon the circuits in the semiconductor device in which the transistors are placed.
In the technique illustrated in JP 1-264264, use is made of different conductor materials for the gate electrode to suppress inter-band tunneling of a selected transistor. Such a technique may complicate the manufacturing process of the semiconductor device by increasing the number of processes to be performed during manufacturing. This may lower yield and may increase manufacturing costs.
In light of the above discussion, it would be desirable to provide a semiconductor device in which inter-band tunneling may be suppressed in selected transistors.
SUMMARY OF THE INVENTION
A semiconductor device according to the present embodiments may include an insulated gate filed effect transistor (IGFET) having a gate insulating layer, a gate electrode, and a source-drain layer. The IGFET may include a bird's beak insulating film in a region in which the gate insulating layer overlaps the source-drain layer. The bird's beak insulating film may have a thickness that is greater than the gate insulating film. In this way, inter-band tunneling may be reduced. A plurality of IGFETs may include bird's beak insulating films having different configurations in accordance with operating conditions of the circuit in which the particular IGFET is included.
According to one aspect of the embodiments, a semiconductor device may include a first IGFET. The first IGFET may include a gate insulating film having a film thickness greater in a first region where a gate electrode overlaps a first source-drain diffusion layer than in a channel region.
According to another aspect of the embodiments, the gate insulating film may have a film thickness greater in a second region where the gate electrode overlaps a second source-drain diffusion layer than in the channel region.
According to another aspect of the embodiments, the gate insulating film may form a bird's beak configuration where the gate insulating film may be thicker at the edge of the gate electrode.
According to another aspect of the embodiments, a second IGFET may have a second gate insulating film that does not have the bird's beak configuration.
Accord
Erdem Fazli
Flynn Nathan J.
NEC Corporation
Sako Bradley T.
Walker Darryl G.
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