Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-03-28
2002-04-16
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S371000, C257S402000, C257S509000
Reexamination Certificate
active
06373106
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and a method for fabricating the same, and in particular to a structure of a MOS transistor and a method for fabricating the same for constituting an input/output buffer circuit having a CMOS structure.
BACKGROUND ART
FIG. 11
shows a sectional view of a conventional NMOS transistor. As shown in
FIG. 11
, the transistor comprises a semiconductor substrate
101
, and element isolation regions
102
formed on the surface of an inactive region of the semiconductor substrate
101
. A P-well
103
is formed up to a predetermined depth from the surface of the semiconductor substrate
101
, and source/drain regions
104
containing N-type impurities are formed on the surface of the semiconductor substrate
101
. A channel region
105
is formed between two source/drain regions
104
. A gate oxide film
106
is formed on the channel region
105
, and a gate electrode
107
is formed on the gate oxide film
106
. Further, a side wall
108
is formed on the lateral section of the gate electrode
107
.
Further, though not illustrated in the sectional view of
FIG. 11
, a contact is formed respectively on the surface of the source/drain regions
104
which appears in cross section in the gate length direction.
Furthermore, in the case of a device in which the NMOS transistor in
FIG. 11
follows a design rule of 0.6 &mgr;m or less, the P-well
103
has at most an impurity concentration of approximately. 3.0 E17/cm
3
.
When the maximum impurity concentration of the P-well
103
is more than 3.0 E17/cm
3
, junction capacitance of an N-type high impurity concentration region of the source/drain regions
104
increases, and as a result, electrical characteristics of the NMOS transistor deteriorate.
Moreover, as the semiconductor device is reduced in size, the impurity concentration in the well tends to be increased. Then, the capacitance of the PN junction between the P-well
103
and the source/drain regions
104
increases. As a result, in the product specification, the criterion of 10 pF or less of input/output capacitance in an input/output buffer portion can be hardly met.
In the following, a method for fabricating a semiconductor device having a CMOS structure including the NMOS transistor in
FIG. 11
is described with reference to FIGS.
12
(
a
) to
12
(
d
).
FIG.
12
(
a
) shows a sectional structure of a transistor to be finally obtained, in which a PMOS transistor forming portion is shown at the left, an NMOS transistor forming portion is shown at the center, and a memory cell forming portion is shown at the right.
First, as shown in FIG.
12
(
b
), a mask
109
is formed on an NMOS transistor forming region and a memory-cell forming region on the semiconductor substrate
101
having the element isolation region
102
serving as an inactive region, and N-type impurities are implanted into a PMOS transistor forming region to form an N-well
110
using the mask
109
as an ion implantation mask. Thereafter, the mask
109
is removed.
Then, as shown in FIG.
12
(
c
), a mask
111
is formed on a PMOS transistor forming region, and P-type impurity ions are implanted into an NMOS transistor forming region and a memory cell forming region to form a P-well
103
by using the mask
111
as an ion implantation mask. Therefore, the mask
111
is removed.
Thereafter, as shown in FIG.
12
(
d
), a mask
112
is formed on PMOS and NMOS transistor forming regions, and impurities are implanted to form a threshold adjustment layer
113
on the surface of an active region of the memory cell forming region. Therefore, the mask
112
is removed.
Further, as shown in FIG.
12
(
a
), gate oxide films
106
and
115
and gate electrodes
107
and
116
are formed in order. The source/drain regions
104
and
114
are formed by implanting N- or P-type impurities into the regions respectively. Then, side walls
108
and
117
are formed on the lateral sections of the gate electrodes
107
and
116
. Thus, the transistor shown in FIG.
12
(
a
) is formed. The threshold adjustment layer
113
is not illustrated in FIG.
12
(
a
) for simplicity.
A semiconductor device comprising transistors of a ICMOS structure may be obtained by following the above fabrication steps. However, as already described, the transistor having the structure shown in FIG.
12
(
a
) has a problem in that capacitance increases in the PN junction formed with a well and a source/drain region.
FIG. 13
shows the structure of a NMOS transistor which has a reduced junction capacitance. The structure of the NMOS transistor shown in
FIG. 13
is different from that of the NMOS transistor shown in
FIG. 11
in that a threshold adjustment layer
105
a
is formed in a region serving as a channel including ends of the two adjacent source/drain regions
104
, and the impurity concentration of the P-well
103
is lower than that of the P-well
103
of the transistor shown in FIG.
11
.
Generally, the threshold adjustment layer
105
a
is formed on the entire surface layer of an active region. However, in this case, the layer
105
a
is formed only on a channel region. Therefore, the impurity concentration of the P-well
103
which is located just under the source/drain region
104
with high concentration N type impurity may be made lower than that of the threshold adjustment layer
105
a.
Thus, the junction capacitance of the source-drain region
104
with the underling P-well
103
is decreased to a certain extent.
A method for fabricating a semiconductor device having a CMOS structure including the transistor shown in
FIG. 13
is shown in FIG.
14
(
a
) to FIG.
14
(
c
).
First, similar steps as shown in FIGS.
12
(
b
) and
12
(
c
) are performed. Then, as shown in FIG.
14
(
a
), a mask
118
is formed on the PMOS transistor forming region and on the NMOS transistor forming region except the channel region thereof. Then, P-type impurity ions are implanted with the mask
118
as an ion implantation mask to form the threshold adjustment layer
105
a
on the channel portion of the NMOS transistor forming region, and also to form the threshold adjustment layer
105
a
with the same concentration on the entire surface of the active region of a memory cell forming region. Thereafter, the mask
118
is removed.
Then, similarly as shown in FIG.
12
(
d
), the mask
112
is formed on the PMOS and NMOS transistor forming regions. Then, ions are additionally implanted into the memory cell region to form the threshold adjustment layer
113
as shown in FIG.
14
(
b
). Thereafter, the mask
112
is removed.
Thereafter, the similar steps as explained with reference to FIG.
12
(
a
) are performed, and thus the semiconductor device having a CMOS structure shown in FIG.
14
(
c
) is obtained. As described above, this structure is different from that of the MOS transistor shown in FIG.
12
(
a
) particularly in that the threshold adjustment layer
105
a
is formed in a region serving as the channel region of an NMOS transistor. Since the threshold adjustment layer
105
a
is formed, the impurity concentration of the P-well
103
underlying the source/drain region may be reduced
104
. Therefore, the junction capacitance between the source/drain region
104
and the P-well
103
may be reduced to a certain extent.
However, in the fabrication method as shown in FIG.
14
(
a
) to
FIG. 14
(
c
), the number of steps is increased compared to the fabrication method of the normal semiconductor device having a CMOS structure such as an SRAM as shown in FIG.
12
. An additional mask (reticle), which is not necessary for normal SRAM fabrication, is required to form the mask
118
and to perform ion implantation. Therefore, fabrication cost is increased as the number of steps is increased.
With regard to the semiconductor substrate
101
as shown in
FIG. 11
to FIG.
14
(
d
), an N-type substrate is used for a CMOSSRAM, and a P-type substrate is used for a Bi-CMOSSRAM which includes bipolar transistors.
Another method for reducing the junction capacitance of a MOS transistor is disclosed in J
Honda Hiroki
Maki Yukio
Loke Steven
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Vu Hung Kim
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