Semiconductor device and method for fabricating the same

Details Semiconductor device and method for fabricating the same Semiconductor device and method for fabricating the same

1999-11-08

2001-11-13

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S175000, C438S176000, C438S072000, C438S069000, C438S029000, C438S167000, C438S514000, C438S525000, C438S527000, C257S098000, C257S213000, C257S336000, C257S350000

Reexamination Certificate

active

06316297

ABSTRACT:

DETAILED DESCRIPTION OF THE INVENTION
The present invention relates to a field-effect semiconductor device using a compound semiconductor substrate, and a method for fabricating the same.
Self-alignment MESFETs using refractory metals as gate electrode materials are relatively easy in the fabrication steps and have thermally stable structures. Because of these advantages the self-alignment MESFETs are widely applied to compound semiconductor integrated circuits and are produced in GaAs gate arrays, amplification ICs for mobile communication apparatuses, such as mobile telephones, etc., ICs for optical communication.
Progress of the recent information communication requires ICs having higher operation speed. For higher operation speed it is one effective means to shorten gate lengths of the used FETS. However, there is a risk that short gate lengths cause the so-called short channel effect. Accordingly, in using short gate lengths it is necessary to design devices in consideration of suppression of the short channel effect.
Under these circumstances, in the compound semiconductor MESFETs the simple structure using a buried P layer has been taken over by BP-LDD structure with LDD (Lightly Doped drain) structure added to the simple structure. However, the conventional BP-LDD structure has become insufficient to suppress the short channel effect in order to meet the requirement of a shorter channel of a 0.2 &mgr;m gate length. Then, the structure additionally including an n″-layer disposed between the so-called n′-layer and channel layer of the BP-LDD structure and having a carrier concentration intermediate concentrations of the n′-layer and the channel layer is proposed (this structure is hereinafter called a developed BP-LDD structure).
A process for fabricating a compound semiconductor MESFET having the conventional developed BP-LDD structure will be explained with reference to
FIGS. 14A-14C
and
15
A-
15
B.
FIGS. 14A-14C
and
15
A-
15
B are sectional views of the semiconductor device in the steps of the method for fabricating the conventional semiconductor device.
First, Mg (magnesium) as an acceptor impurity and a Si (silicon) as a donor impurity are ion-implanted into a MESFET region of a GaAs substrate
100
to form a buried p-layer
102
of the Mg-doped layer and an n-channel layer
104
of the Si-doped layer.
Then, a WSi (tungsten silicide) film is deposited on the entire surface by, e.g., sputtering and patterned to form a gate electrode
106
of the WSi film (FIG.
14
A).
Then, resist
108
is formed by the usual lithography techniques, covering the region other than the MESFET region.
Next, Si is ion-implanted with the resist
108
and the gate electrode
106
as a mask to form an n″-layer
110
in the GaAs substrate
100
(FIG.
14
B).
Then, after the resist
108
is removed, an SiN (silicon nitride) film is deposited on the entire surface by, e.g., CVD method to form a through film
112
of the SiN film.
Next, a resist
114
is formed by the usual lithography techniques, covering the region other than the MESFET region.
Then, Si is ion-implanted with the resist
114
, the gate electrode
106
, the through film
112
on the sidewall of the gate electrode
106
as a mask to form an n′-layer
116
spaced from the edges of the gate electrode
106
by a distance corresponding to a film thickness of the through film
112
(FIG.
14
C).
Next, an insulation film is deposited on the entire surface and etched back to form on the sidewall of the gate electrode
106
a sidewall insulation film
118
having a width larger than the film thickness of the through film
112
.
Then, a resist
120
is formed by the usual lithography techniques, covering the region other than the MESFET region.
Next, Si is ion-implanted with the resist
120
, the gate electrode
106
and the sidewall insulation film
118
as a mask to form an n
+
-layer
122
spaced from the sidewall of the gate electrode
106
by a distance corresponding to the width of the sidewall insulation film
118
(FIG.
15
A).
Next, after the sidewall insulation film
118
is removed, a heat treatment for activating the impurities is performed.
Then, an ohmic electrode
124
are formed on the n
+
-layer
122
, and the MESFET is completed (FIG.
15
B).
Thus, the MESFET of the developed BP-LDD structure including the source/drain diffusion layer formed of the n″-layer
110
, the n′-layer
116
and the n
+
-layer
122
is formed.
Japanese Patent Laid-Open Publication No. 153474/1982 proposes, as one technique for forming the LDD structure, a technique for simultaneously forming two diffusion layers having different carrier profiles by once ion implantation. In this technique, when a gate electrode is patterned with a resist as a mask, the gate electrode is processed to have a smaller width than the resist to form an eave-shaped resist film on the gate and in this state the ion implantation is performed, whereby an impurity is implanted shallow near the gate electrode below the eave-shaped resist film and deep in a region spaced from the eave-shaped resist film.
A method for fabrication a MESFET using the eave-shaped resist film formed on the gate electrode will be explained with reference to
FIGS. 16A-16C
and
17
A-
17
B.
FIGS. 16A-16C
and
17
A-
17
B are sectional views of another conventional semiconductor device in the steps of the method for fabricating the same.
First, Mg as an acceptor impurity and Si as a donor impurity are ion-implanted into a MESFET region of a GaAs substrate
100
to form a buried p-layer
102
of the Mg-doped layer, and an n-channel layer
104
of the Si-doped layer.
Then, a WSi film
126
is deposited on the entire surface by, e.g., sputtering method (FIG.
16
A).
Then, a resist having a pattern for forming a gate electrode is formed on the WSi film
126
by the usual lithography techniques.
Next, the WSi film
126
is dry-etched with the resist as a mask under conditions where the etching progresses also horizontally to the GaAs substrate
100
. Thus, the gate electrode
106
formed of the WSi film
126
and the eave-shaped resist film
128
formed on the gate electrode
106
are formed (FIG.
16
B).
Next, Si is ion-implanted with the eave-shaped resist film
128
and the gate electrode
106
as a mask. In this ion implantation, because of the eave-shaped resist film
128
formed on the gate electrode
106
, the Si ions are implanted in a vicinity of the edge of the gate electrode
106
below the eave-shaped resist film
128
substantially at lower acceleration energy and in a smaller dose. Accordingly, an n′-layer
116
which has a lower concentration and is shallow and an n
+
-layer
122
which has a higher concentration and is deep are formed (FIG.
16
C).
Then, a resist
130
covering the MESFET region and exposing a device isolation region is formed by the usual lithography techniques.
Then, p-type impurity is ion-implanted with the resist
130
as a mask to form a device isolation layer
132
(FIG.
17
A).
Then, an ohmic electrode
124
is formed on the n
+
-layer
122
, and the MESFET is completed (FIG.
17
B).
Thus, MESFET of the BP-LDD structure having the source/drain diffusion layer form of the n′-layer
116
and the n
+
-layer
122
is fabricated by a small number of fabrication steps.
In order to suppress the short channel effect it is effective to shallow the channel layer. To thin the channel layer in accordance with a scaling rule the n′-layer and the n
+
-layer must be also shallowed. However, shallowing these layer of the diffusion layer makes small a sectional area of a region between the source and the drain where current flows. Accordingly, it is considered that a resistance value will increase, and a channel conductance Gm will not be improved, which will make improvement of the FET by shortening the channel insufficient.
On the other hand, when impurity concentrations of the respective doped layers are increased to reduce a resistance value, because of the structure of the ME

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