Semiconductor device and method for fabricating the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S536000, C257S350000, C257SE21431, C257SE21438, C257SE27016

Reexamination Certificate

active

07843013

ABSTRACT:
A semiconductor device includes: an isolation region formed in a semiconductor substrate; active regions surrounded by the isolation region and including p-type and n-type regions, respectively; an NMOS transistor formed in the active region including the p-type region and including an n-type gate electrode; a PMOS transistor formed in the active region including the n-type region and including a p-type gate electrode; and a p-type resistor formed on the isolation region. The p-type resistor has an internal stress greater than that of the p-type gate electrode.

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Ota, K. et al., “Novel Locally Strained Channel Technique for High Performance 55nm CMOS,” IDEM 2002, p. 27.
Ortolland, C. et al., “Stress Memorization Technique (SMT) Optimization for 45nm CMOS,”VLSI 2006, pp. 96-97.

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