Semiconductor device and method for fabricating the same

Details Semiconductor device and method for fabricating the same Semiconductor device and method for fabricating the same

2006-03-21

2006-03-21

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257S344000

Reexamination Certificate

active

07015554

ABSTRACT:
Impurities for threshold voltage adjustment are implanted using a resist film and a protective dielectric as implantation masks from directions inclined at 10° through 30° with respect to the direction vertical to the principal surface of a semiconductor substrate1when viewed in cross section taken along the gate width direction. Thus, first low-concentration impurity implantation regions are formed to overlap each other in the central part of an active region for a memory cell MIS transistor Mtrs of an SRAM. Furthermore, after an isolation is formed, a second low-concentration impurity implantation region is formed in an active region for each of MIS transistors Ltr, Mtrs and Mtrl by implanting impurity ions without using implantation masks. The MIS transistors Ltr, Mtrs and Mtrl formed after the completion of the fabricating process have substantially the same threshold voltage.

REFERENCES:
patent: 6642589 (2003-11-01), Wada et al.
patent: 6667524 (2003-12-01), Sakakibara
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patent: 2003-031682 (2003-01-01), None
C. Chen, C.Y. Chang, J.W. Chou, C. T. Huang, K.C. Lin, Y. C. Cheng, and C. Y. Lin, “Optimization of Short Channel Effect by Arsenic P-Halo Implant Through Polysilicon Gate for 0.12 um P-MOSFET,” Proc. IEDM 2000 (Jun. 24, 2000), pp. 44-47.

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