Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-16
2004-08-31
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000, C257SE21158, C257SE21632, C257SE21637, C257SE23152, C257SE23193, C257SE27108
Reexamination Certificate
active
06784472
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically a semiconductor device including the gate electrodes formed of a metal-based material and a method for fabricating the semiconductor device.
BACKGROUND ART
Recently, information amounts for electronic equipments to process are on increase, and larger-scale, higher speed semiconductor integrated circuits are required. This is accompanied by micronization and speed-up of semiconductor devices.
Conventionally, polysilicon has been widely used in the gate electrodes of MIS (Metal Insulator Semiconductor) transistors, and due to the high resistance of polysilicon, the gate electrodes have large signal delays. As semiconductor devices are more micronized, the signal delay of the gate electrodes becomes more serious. It is necessary to make the gate electrodes less resistant.
As techniques for making the gate electrodes less resistant, semiconductor devices of the polycide structure and the salicide (Self-Aligned Silicide) structure are proposed. Recently, as the semiconductor devices are further micronized, the gate electrodes are required to be less resistant.
To make the gate electrodes less resistant it is proposed to use metals as materials of the gate electrodes. The conventionally used processes cannot be used in cases of using metals as materials of the gate electrodes. When the gate electrodes are formed of a metal, the heat processing for activating the sources/drains often damages the gate electrodes or increases leak current of the gate insulation film.
A technique which can prohibit the gate electrode damage and the gate leak current increase even in a case the gate electrodes are formed of a metal is proposed in the specification of Japanese Patent Laid-Open Publication No. Hei 10-189966/1998 and International Electron Device Meeting, TECHNICAL DIGEST, 1998, p.777-780.
The proposed semiconductor device fabrication method will be explained with reference to
FIGS. 24A
to
25
B.
FIGS. 24A
to
25
B are sectional views of the semiconductor device in the steps of the fabrication method.
As shown in
FIG. 24A
, first dummy gate electrodes
148
are formed of polysilicon on a semiconductor substrate
110
with a dummy gate insulation film
146
formed therebetween. Next, a dopant is implanted shallowly in the semiconductor substrate by self-alignment with the dummy gate electrodes to form a shallow doped-region
136
a
. A sidewall insulation film
124
is formed on the side walls of the dummy gate electrodes
148
. A dopant is implanted deeply in the semiconductor substrate by self-alignment with the dummy gate electrodes with the sidewall insulation film
124
formed on to form a deep doped-region
136
b
. Thus a source/drain diffused layer
136
is formed of the shallow doped-region
136
a
and the deep doped-region
136
b
. Next a high-temperature thermal processing is performed for activating the sources/drains.
Next, an inter-layer insulation film
140
is formed on the entire surface and planarized until the upper surfaces of the dummy gate electrodes
148
are exposed (see FIG.
24
B).
Next, the dummy gate electrodes
148
and the dummy gate insulation film
146
are etched to form openings
156
down to the semiconductor substrate
110
(see FIG.
24
C).
Then, an insulation film
128
is formed on the entire surface. Then, a TiN film
130
is formed on the entire surface (see FIG.
25
A).
Next, the TiN film
130
and the insulation film
128
are polished by CMP (Chemical Mechanical Polishing) until the surface of the inter-layer insulation film
140
is exposed. Thus, the gate insulation film
128
, and a gate electrode
134
of the TiN film are buried in the openings
156
(see FIG.
25
B).
In the semiconductor device fabricated by the proposed fabrication method, after the high-temperature thermal processing for activating the sources/drains, the dummy gate electrodes and the dummy gate insulation film are etched, and then the gate insulation film and the gate electrodes are formed, whereby even in a case that the gate electrodes are formed of a metal, the gate electrode damage and gate leak current increase can be precluded.
On the other hand, recently semiconductor devices of the dual gate structure have been proposed as a technique which can realize low threshold voltages while depressing the short channel effect of the transistors. A semiconductor device of the dual gate structure is a semiconductor device having the gate electrodes of the p-channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors) and the gate electrodes of the n-channel MISFETs formed of materials different from each other. Generally, the gate electrodes of the n-channel MISFETs are formed of n-type polysilicon, and the gate electrodes of the p-channel MISFETs are formed of p-type polysilicon. Semiconductor devices of such dual gate structure can realize low threshold volatges while depressing the short channel effect of the transistors, which is useful especially in semiconductor devices whose gate lengths are below 0.25 &mgr;m.
Here, it is considered to fabricate a semiconductor device of the dual gate structure by using the method shown in
FIGS. 24A
to
25
B.
FIG. 26
is a sectional view of the semiconductor device of the dual gate structure fabricated by using the proposed method.
As shown in
FIG. 26
, an element isolation region
112
for defining element regions is formed on a semiconductor substrate
110
. An inter-layer insulation film
140
is formed on the semiconductor substrate
110
with the element isolation region
112
formed on.
A gate insulation film
116
and a gate electrode
122
of Pt are buried in the inter-layer insulation film
140
in a region
114
a
for a p-channel MISFET to be formed in. A gate insulation film
128
and a gate electrode
134
of TiN film are formed in the inter-layer insulation film
140
in a region
114
b
for an n-channel MISFET to be formed in. Thus, the gate electrode
122
of the p-channel MISFET
138
a
and the gate electrode
134
of the n-channel MISFET
138
b
form the semiconductor device using metal-based materials different from each other.
However, in the semiconductor device shown in
FIG. 26
, because of the gate insulation film
128
formed on the side wall of the gate electrodes
134
, the gate electrode
122
and the gate electrode
134
are insulated from each other by the gate insulation film
128
. Accordingly, the semiconductor device shown in
FIG. 26
cannot normally operate.
Here, it is also considered to connect the gate electrode
122
and the gate electrode
134
by means of an interconnection electrode.
FIG. 27
is a plan view of the semiconductor device having the gate electrodes interconnected with each other by means of the interconnection electrode.
As shown in
FIG. 27
, a contact region
122
a
is formed in the gate electrode
122
, and a contact region
134
a
is formed in the gate electrode
134
. A source/drain diffused layer
126
is formed in the semiconductor substrate on both sides of the gate electrode
122
, and a source/drain diffused layer
136
is formed in the semiconductor substrate on both sides of the gate electrode
134
.
An interconnection electrode
135
for interconnecting the contact region
122
a
and the contact region
134
a
is formed on the contact region
122
a
and the contact region
134
a
. The thus formed interconnection electrode
135
can electrically interconnect the gate electrode
122
and the gate electrode
134
with each other.
However, in the semiconductor device shown in
FIG. 27
, the contact regions
122
a
,
134
a
must be formed respectively in the gate electrode
122
and the gate electrode
134
, which restricts the freedom degree of the design and makes it difficult to integrate the semiconductor device vertically as viewed in the drawing. Thus, the semiconductor device shown in
FIG. 27
ignores the original significance of providing a micronized semiconductor device.
Furthermore, the gate electrode
Iriyama Yasunori
Izawa Tetsuo
Fujitsu Limited
Niebling John F.
Pompey Ron
Westerman Hattori Daniels & Adrian LLP
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