Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-08-12
2004-12-21
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S370000, C257S371000, C257S375000
Reexamination Certificate
active
06833591
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more specifically a semiconductor device including contact holes in alignment with a base pattern and a method for fabricating the same.
2. Description of the Related Art
As LSIs become larger-scaled, more micronization of devices is pursued.
To realize semiconductor integrated circuits including gates, interconnections and contact holes of more micronized dimensions, conventionally wavelengths of the exposure radiation for the photolithography have been made shorter to thereby improve resolving power.
While minimum resolved dimensions have been thus diminished, various device structures which decrease margins for alignment between lithography steps have been studied. In place of diminishing dimensions of patterns to be formed, dimensions of devices have been decreased.
As such structure, self-aligned contact (hereinafter called SAC), for example, is known.
The conventional SAC structure will be explained in comparison with a case including no SAC structure.
As shown in
FIG. 24A
, in a case that two gate electrodes
208
are formed on a silicon substrate
200
, and an inter-layer insulation film
226
is formed on the gate electrodes
208
, when a contact hole
228
is opened between the two gate electrodes
208
down to the silicon substrate
200
, the gate electrodes
208
must be arranged, considering in advance alignment precision for opening the contact hole
228
.
That is, gaps (a) between the contact hole
228
and the gate electrodes
208
, which are larger than an alignment precision must be ensured so that when a conducting film is buried in the contact hole
228
, the conducting film does not short-circuit with the gate electrodes
208
(FIG.
24
B). Accordingly, a gap between the gate electrodes
208
is subject to the contact hole, which hinders further micronization.
In contrast to this, as shown in
FIG. 24C
, gate electrodes
208
are covered with an insulation film
230
having etching selectivity with the inter-layer insulation film
226
. The insulation film
230
functions as an etching stopper in etching the inter-layer insulation film
226
to thereby protect the insulation film
232
(on the gate electrodes
208
and on the side walls) from excessive etching, so that the gate electrodes
208
are never exposed in the opening
228
by over-etching of the insulation film
232
. Accordingly, a conducting film buried in the contact hole
228
is not short-circuited with the gate electrodes
208
.
Thus, when disalignment occurs in the lithography step of forming the contact hole
228
, an opening down to a silicon substrate
200
, is defined only by the gate electrodes
208
and the insulation film
230
, and even when the contact hole
228
is a little disaligned with the gate electrodes
208
, the opening can be formed in a prescribed position (FIG.
24
D). This enables the device to be micronized.
A method for fabricating the conventional semiconductor device including the SAC structure will be specifically explained by means of a structure of the cell array region of a DRAM with reference to
FIGS. 25 and 26
.
First, a device isolation film
202
is formed on a silicon substrate
200
by, e.g., the usual LOCOS method.
Then a gate insulation film
206
is formed in a device region
204
by, e.g., thermal oxidation.
Subsequently gate electrodes
208
are formed on the gate insulation film
206
. Insulation films of, e.g., doped polycrystalline silicon film and silicon oxide film are continuously deposited by CVD, and the laid films are processed in the same pattern, and the gate electrodes
208
having the top surfaces covered with an insulation film
210
are formed (FIG.
25
A).
Then, ions are implanted with the gate electrodes
208
as a mask to form in the device region an impurity-doped region
212
which is to be a low-concentration diffused layer of LDD structure.
Next, an insulation film
214
of, e.g., silicon oxide film is deposited on the entire surface (FIG.
25
B).
Subsequently, the insulation film
214
is etched back by anisotropic etching to form sidewall insulation films
216
on the side walls of the gate electrodes
208
.
Subsequently, ions are implanted with the gate electrodes and the sidewall insulation films as a mask to form an impurity doped region
218
which is to be a high-concentration diffused layer of LDD structure (FIG.
25
C).
Then, the implanted impurity is activated by, e.g., a thermal treatment at 1000° C. for 10 seconds to form a source/drain diffused layers
220
,
222
of LDD structure.
Then, an etching stopper film
224
of, e.g., silicon nitride film is deposited. The etching stopper film
224
is to be a protection film for protecting the base from being etched off when contact holes are opened in an inter-layer insulation film to be deposited on the etching stopper film
224
.
Subsequently, an insulation film of, e.g., silicon oxide film is deposited and has the surface polished by, e.g., CMP (Chemical Mechanical Polishing) to form an inter-layer insulation film
226
having the surface planarized (FIG.
26
A). The inter-layer insulation film
226
is formed of a material providing an etching selectivity with respect to the etching stopper film
224
.
Subsequently, contact holes
228
opened on the source/drain diffused layers
220
,
222
are formed.
When the contact holes
228
are etched, the inter-layer insulation film
226
is etched under conditions for etching the silicon oxide film, which can provide a sufficient selective ratio with respect to silicon nitride film, whereby even when parts of the contact holes
228
are extended over the gate electrodes
208
, the etching stopper film
224
is not substantially etched.
Thus, the sidewall insulation films
216
, and the insulation film
210
on the gate electrodes
208
are not excessively etched, and the contact holes can be stably opened.
Then, the etching stopper film
224
is etched to expose the source/drain diffused layers
220
,
222
in the contact holes
228
(FIG.
26
C).
In etching the etching stopper film
224
it is usual that anisotropic etching is not used, but wet etching in which the etching isotropically goes on is used. There are two reasons for this. One of the reasons is that the etching stopper film remaining as the sidewall insulation films narrow the contact regions, which increases contact resistance. The other of the reasons is to prevent the silicon substrate from being damaged by the anisotropic etching and having crystal defects.
The contact holes
228
are thus opened, whereby regions where the contact holes
228
are formed can overlap the gate electrodes
208
, so that even when a resist pattern is a little disaligned by disalignment in the lithography step, the contact holes
228
can be opened in alignment with the gate electrodes
208
or the device isolation film
202
.
As LSIs are higher integrated, new problems of the method for fabricating the above-described conventional semiconductor device have been made clear.
To attain higher integration of a semiconductor device it is necessary to form a larger number of transistors in a smaller region. The gap between the gate electrodes
208
is made smaller. In DRAMs, for example, the pattern size is about 0.7 times every generation, and is diminished by about ½ in two generations. On the other hand, to sufficiently function the etching stopper film
224
in the method for fabricating the semiconductor device shown in
FIGS. 25 and 26
, substantially the same film thickness as in the conventional semiconductor device is required.
When a semiconductor device is fabricated with these conditions satisfied, the contact region between the gate electrodes
208
is completely filled with the etching stopper film
224
(FIG.
27
).
Here, to form the contact hole
228
in the contact region between the gate electrodes
208
it is necessary to remove the etching stopper film
224
filled in the contact region, but it is very difficult to rem
Armstrong Kratz Quintos Hanson & Brooks, LLP
Fujitsu Limited
Wojciechowicz Edward
LandOfFree
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