Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-12-28
2004-08-03
Hu, Shouxiang (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S217000, C438S289000, C438S298000, C438S910000
Reexamination Certificate
active
06770517
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device formed on an insulator substrate or on an SOI (silicon on insulator) substrate in which a single crystalline silicon thin film is formed on an insulator film, and also related to a method for fabricating the semiconductor device.
In recent years, in the field of portable communication units such as cellular phone units, a device operating with low voltage, high speed, and low consumption power has been demanded. In order to satisfy these requirements or realize these properties, various attempts have been vigorously carried on by forming a transistor on an insulator substrate or on an SOI substrate, in which a semiconductor film is formed on an insulator film (hereinafter, simply referred to as an SOI transistor), and thereby reducing the parasitic capacitance or the like.
The structure of the conventional SOI transistor will be described with reference to the drawings.
FIG. 11
is a cross-sectional view of the conventional SOI transistor.
As shown in
FIG. 11
, an insulator layer
702
of an oxide film is formed on a p-type single crystalline silicon substrate
701
. A silicon layer
703
used as the active region of the transistor is formed on the insulator layer
702
. A LOCOS film
704
is formed for the purpose of isolating respective regions of the silicon layer
703
from each other just like islands. A gate oxide film
705
is selectively formed on each of the isolated regions of the silicon layer
703
, and a gate electrode
707
of a polysilicon film is formed on the gate oxide film
705
. Sidewalls
708
are formed on the sides of the gate electrode
707
. A channel region
714
is formed in the silicon layer
703
just under the gate oxide film
705
and sandwiched by a source region
709
and a drain region
710
, which contain a high-concentration impurity. An interlevel insulator film
711
of a BPSG film or the like, contact holes
712
, and a metal interconnection layer
713
as an electrode are formed on the LOCOS film
704
, the gate electrode
705
, the source region
709
and the drain region
710
.
FIGS. 12
a
to
12
e
are cross-sectional views depicting the fabricating process of the conventional SOI transistor.
SOI substrates can be classified into SIMOX substrates, bonded substrates, and other types of substrates. The SOI substrate to be described herein has a three-layer structure: a silicon substrate
701
; an insulator layer
702
of a silicon oxide film
701
formed thereon; and a silicon layer
703
formed further thereon as the uppermost layer.
First, as shown in
FIG. 12
a
, the LOCOS film
704
is formed by selective oxidation technique by using a mask consisting of a pad oxide film
721
and a silicon nitride film
722
, thereby isolating the respective regions of the silicon layer
703
from each other just like islands.
Then, as shown in
FIG. 12
b
, after removing the pad oxide film
721
and the nitride film
722
, a p-type impurity is implanted in order to control the threshold value.
Next, as shown in
FIG. 12
c
, after forming a silicon oxide film and a polysilicon film in this order on the silicon layer
703
, the gate oxide film
705
and the gate electrode
707
are formed by patterning, and then the sidewalls
708
are formed on the sides of the gate electrode
707
.
Subsequently, as shown in
FIG. 12
d
, n-type impurity ions are implanted into the silicon layer
703
by using the gate electrode
707
as mask, thereby forming the source region
709
and the drain region
710
in a self-aligned manner.
Finally, as shown in
FIG. 12
e
, after the interlevel insulator film
711
is deposited, the contact holes
712
are formed in the interlevel insulator film
711
. After the metal interconnection layer
713
is deposited to fill up the contact holes
712
and to extend over the interlevel insulator film
711
, the layer
713
is patterned.
By performing these process steps, the SOI transistor shown in
FIG. 11
is completed.
However, such an n-channel-type SOI transistor where the silicon layer formed on the SOI substrate is isolated by the LOCOS film and the potential of the channel region is electrically floating, has the following two problems.
Firstly, in an MOS transistor, if the drain voltage is high enough, the electrons implanted into the channel region from the source region have so high energy in a region near the drain that that they cause impact ionization and generate hole-electron pairs. In a normal bulk transistor, generated electrons move to the drain region while the holes move to the inside of the substrate, causing not so serious problem. However, in the SOI transistor where the channel region
714
is electrically floating, holes are accumulated in a region of the electrically floating channel region
714
in the vicinity of the source region
709
. Then, the accumulated holes lower the energy barrier between the source region and the channel region, causing a bipolar operation due to the amplification action similar to that of a bipolar transistor and increasing the current flowing in the channel region. This causes a problem that the source-drain breakdown voltage decreases.
Secondly, the use of a LOCOS film for the isolation of transistors generally causes a bird's beak in the isolated area. Thus, in the process step shown in
FIG. 12
b
, the impurity concentration implanted into the portion of the silicon layer
703
under the bird's beak becomes lower than that of the other channel region
714
. As a result, a parasitic transistor, i.e., a so-called an edge transistor, where the portion under the bird's beak becomes a channel region, is formed.
FIGS. 13
a
and
13
b
are respectively a plan view and a cross-sectional view taken along the line XIII—XIII for illustrating edge transistors formed on both ends of a main transistor, which is an original SOI transistor. As shown in
FIG. 13
a
, in addition to the current (see the bold arrow in
FIG. 13
a
) flowing through the main transistor, current also flows through the edge transistors generated on both ends (see the fine arrows in
FIG. 13
a
). In an SOI transistor having no well structure, since the impurity concentration in the silicon layer just under the bird's beak is lower than that of the channel region, the threshold value of the edge transistors becomes lower than that of the main transistor. Consequently, as shown in
FIG. 14
, if the voltage to be applied to the gate electrode is being increased, the edge transistors are turned ON before the main transistor is turned ON. As a result, the sub threshold property has a hump, causing a problem that the leakage current during the standby mode of the transistor increases.
SUMMARY OF THE INVENTION
An object of the present invention is to improve the reliability of an SOI transistor, formed to be isolated by a LOCOS film on a region on an SOI substrate and having a channel region with an electrically floating potential, by increasing source/drain breakdown voltage and by preventing leakage current from increasing during the stand-by thereof.
In order to accomplish this object, the present invention provides a region for eliminating carriers in the vicinity of the channel region of the SOI transistor such as a lattice defect region containing a lot of lattice defects functioning as the center of recombination, and/or a high-concentration diffusion region constituting a diode between the source/drain regions.
The semiconductor device of the invention includes: a substrate having an insulator layer thereon; a semiconductor layer of a first conductivity type formed on the insulator layer, part of the semiconductor layer functioning as a channel region; a gate insulator film formed on the channel region of the semiconductor layer; a gate electrode formed on the gate insulator film; source/drain regions of a second conductivity type formed in the semiconductor layer so as to sandwich the channel region therebetween; and a hole-eliminating region having a function of preventing the accumulation of holes of hole-
Fujimoto Hiromasa
Hirai Takehiro
Hori Atsushi
Nakaoka Hiroaki
Uehara Takashi
Hu Shouxiang
Matsushita Electric - Industrial Co., Ltd.
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