Semiconductor device and method for fabricating the same

Details Semiconductor device and method for fabricating the same Semiconductor device and method for fabricating the same

2002-09-23

2004-07-13

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S624000

Reexamination Certificate

active

06762120

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including metal interconnects having an air gap and a method for fabricating the same.
A semiconductor device including metal interconnects having an air gap and a method for fabricating the same according to a first conventional example will now be described with reference to
FIGS. 11A through 11C
,
12
A through
12
C,
13
A through
13
C and
14
A through
14
C.
First, as shown in
FIG. 11A
, a lower interlayer insulating film
11
of an insulating material is formed on a semiconductor substrate
10
by chemical vapor deposition (CVD) or spin coating. Thereafter, although not shown in the drawing, a plug connected to the semiconductor substrate
10
or an interconnect formed on the semiconductor substrate
10
is formed in the lower interlayer insulating film
11
.
Next, a first barrier metal layer
12
, a first metal film
13
and a second barrier metal layer
14
are successively deposited on the lower interlayer insulating film
11
. The first barrier metal layer
12
and the second barrier metal layer
14
are deposited by sputtering, and the first metal film
13
is formed by the sputtering, CVD or plating. Thereafter, an insulating film
15
is formed on the second barrier metal layer
14
by the CVD or spin coating.
Then, as shown in
FIG. 11B
, after forming a first resist pattern
16
on the insulating film
15
by lithography, the insulating film
15
is dry etched by using the first resist pattern
16
as a mask. Thus, plug openings
17
are formed in the insulating film
15
as shown in FIG.
11
C.
Next, as shown in
FIG. 12A
, a second metal film
18
is deposited on the insulating film
15
so as to fill the plug openings
17
by the sputtering, CVD or plating.
Then, as shown in
FIG. 12B
, an unnecessary portion of the second metal film
18
present on the insulating film
15
is removed by chemical mechanical polishing (CMP), thereby forming contact plugs
19
from the second metal film
18
. Thereafter, as shown in
FIG. 12C
, the insulating film
15
is dry etched so as to reduce the thickness thereof. Thus, upper portions of the contact plugs
19
protrude from the insulating film
15
.
Subsequently, as shown in
FIG. 13A
, a second resist pattern
20
is formed on the insulating film
15
by the lithography. Then, as shown in
FIG. 13B
, the insulating film
15
is dry etched by using the second resist pattern
20
as a mask, thereby forming a patterned insulating film
15
A in the pattern of interconnects.
Next, as shown in
FIG. 13C
, the second barrier metal layer
14
, the first metal film
13
and the first barrier metal layer
12
are dry etched by using the second resist pattern
20
, the patterned insulating film
15
A and the contact plugs
19
as a mask, thereby forming metal interconnects
21
composed of a patterned second barrier metal layer
14
A, a patterned first metal film
13
A and a patterned first barrier metal layer
12
A. In this manner, a remaining resist
22
in the shape of ridges with facets inclined at approximately 45 degrees is formed on the patterned insulating film
15
A and facets are also formed in top portions of the patterned insulating film
15
A.
In the first conventional example, the metal interconnects
21
are formed by dry etching the second barrier metal layer
14
, the first metal film
13
and the first barrier metal layer
12
with the second resist pattern
20
, the patterned insulating film
15
A and the contact plugs
19
used as the mask. Instead, the metal interconnects
21
may be formed by dry etching the second barrier metal layer
14
, the first metal film
13
and the first barrier metal layer
12
with the patterned insulating film
15
A and the contact plugs
19
used as the mask after removing the second resist pattern
20
by ashing. In this case, the patterned insulating film
15
A is sputtered during the dry etching for forming the metal interconnects
21
, and hence, facets are also formed in the top portions of the patterned insulating film
15
A.
Next, as shown in
FIG. 14A
, portions of the lower interlayer insulating film
11
between the metal interconnects
21
are trenched by the dry etching. Thus, the remaining resist
22
is removed but is transferred to the patterned insulating film
15
A, resulting in enlarging the facets of the patterned insulating film
15
A.
Then, as shown in
FIG. 14B
, an upper interlayer insulating film
23
is formed over the contact plugs
19
, the metal interconnects
21
and the lower interlayer insulating film
11
by the CVD and air gaps
24
are formed in the upper interlayer insulating film
23
between the metal interconnects
21
.
Subsequently, as shown in
FIG. 14C
, the upper interlayer insulating film
23
is planarized by the CMP. Thus, the interconnects having the air gaps are completed. Thereafter, the aforementioned sequence is repeated, so as to fabricate a semiconductor device having a multi-layer interconnect structure.
Since the upper interlayer insulating film
23
is formed with the facets formed in the top portions of the patterned insulating film
15
A in the first conventional example, the upper interlayer insulating film
23
tends to enter the portions between the metal interconnects
21
. Therefore, the top portion of the air gap
24
(a portion with a triangular cross-section) is positioned at substantially the same level as the metal interconnect
21
.
A semiconductor device including metal interconnects having an air gap and a method for fabricating the same according to a second conventional example will now be described with reference to
FIGS. 15A through 15C
,
16
A through
16
C,
17
A through
17
C,
18
A and
18
B.
First, as shown in
FIG. 15A
, a lower interlayer insulating film
31
of an insulating material is formed on a semiconductor substrate
30
by the CVD or spin coating. Thereafter, although not own in the drawing, a plug connected to the semiconductor substrate
30
or an interconnect formed on the semiconductor substrate
30
is formed in the lower interlayer insulating film
31
.
Next, a first barrier metal layer
32
, a first metal film
33
and a second barrier metal layer
34
are successively deposited on the lower interlayer insulating film
31
. The first barrier metal layer
32
and the second barrier metal layer
34
are deposited by the sputtering, and the first metal film
33
is formed by the sputtering, CVD or plating. Thereafter, an insulating film
35
is formed on the second barrier metal layer
34
by the CVD or spin coating.
Then, after forming a first resist pattern
36
on the insulating film
35
by the lithography as shown in
FIG. 15B
, the insulating film
35
is dry etched by using the first resist pattern
36
as a mask so as to form a patterned insulating film
35
A in the pattern of interconnects as shown in FIG.
15
C. Thereafter, the first resist pattern
36
is removed by the ashing.
Next, as shown in
FIG. 16A
, the second barrier metal layer
34
, the first metal film
33
and the first barrier metal layer
32
are dry etched by using the patterned insulating film
35
A as a mask, thereby forming metal interconnects
37
composed of a patterned second barrier metal layer
34
A, a patterned first metal film
33
A and a patterned first barrier metal layer
32
A. Thus, the patterned insulating film
35
A is sputtered during the dry etching for forming the metal interconnects
37
, and hence, facets are formed in the top portions of the patterned insulating film
35
A.
Then, as shown in
FIG. 16B
, portions of the lower interlayer insulating film
31
between the metal interconnects
37
are trenched by the dry etching. Thus, the patterned insulating film
35
A is reduced in its thickness with the facets formed in the top portions thereof.
Subsequently, as shown in
FIG. 16C
, an upper interlayer insulating film
38
is formed over the metal interconnects
37
and the lower interlayer insulating film
31
by the CVD and air gaps
39
are formed in the upper interlayer insulating film
38
between

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