Semiconductor device and method for fabricating the same

Details Semiconductor device and method for fabricating the same Semiconductor device and method for fabricating the same

2002-12-23

2004-07-13

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

C438S309000, C438S317000, C438S318000, C438S320000, C438S047000

Reexamination Certificate

active

06762106

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices functioning as heterojunction bipolar transistors including epitaxial base layers, and methods for fabricating the same.
Operation speed of silicon bipolar transistors has been increased through use of progress in microfabrication and self-alignment technique. In order to further increase the operation speed, research and development of bipolar transistors with heterojunction (heterojunction bipolar transistors) has been actively conducted. More specifically, in recent years, active attempts have been made to use SiGe mixed crystalline semiconductors (i.e., SiGe heterojunction bipolar transistors which will be herein referred to as “SiGe-HBTs”) as base layers.
FIGS. 14A through 14F
are cross-sectional views illustrating a typical method for fabricating an SiGe-HBT using a known selective SiGe epitaxial growth technique.
First, in a process step shown in
FIG. 14A
, an N
+
impurity layer
102
is formed in an upper part of a p-type silicon substrate
101
by ion implantation, and then an N
−
epitaxial layer
103
is formed thereon. Thereafter, an isolation oxide film
104
is formed using a trench formation technique and an oxide film embedding technique.
Next, in a process step shown in
FIG. 14B
, an oxide film
105
and a nitride film
106
are deposited by CVD in this order over the substrate, and then using a photolithography technique and an etching technique, a collector opening
115
(i.e. a region where epitaxial growth is to be performed and which will be herein also referred to as a “epitaxial growth region”) is formed in the nitride film
106
. Furthermore, the oxide film
105
is wet-etched to remove an exposed part thereof corresponding to the collector opening
115
.
Next, using molecular beam epitaxy (MBE), ultra-high vacuum chemical vapor deposition (UHV-CVD) or low-pressure chemical vapor deposition (LP-CVD), an SiGe layer
107
including an Si cap layer, an SiGe spacer layer and a graded SiGe layer is epitaxially grown in an epitaxial growth region corresponding to the collector opening
115
. At this point, use of the selective SiGe epitaxial growth technology can prevent deposition of a polycrystalline layer on the nitride film
106
.
Next, in a process step shown in
FIG. 14C
, an oxide film
109
is deposited over the substrate and then is partially removed through a photolithography technique and an etching technique so that part of the oxide film
109
is left on the center portion of the Si/Ge layer
107
.
Thereafter, in a process step shown in
FIG. 14D
, a polysilicon film
110
that is to serve as a base lead-electrode is deposited over the substrate, and then ions of boron as an impurity are implanted into the polysilicon film
110
. Thereafter, an oxide film
111
is deposited on the polysilicon film
110
. Then, an emitter opening
116
is formed in the oxide film
111
and the polysilicon film
110
through a photolithography technique and an etching technique.
Next, in a process step shown in
FIG. 14E
, an oxide film and a nitride film are deposited over the substrate, and then anisotropic dry etching is performed to form an oxide film sidewall
118
and a nitride film sidewall
112
on each side wall of a lamination of the oxide film
111
and the polysilicon film
110
. Furthermore, the oxide film
109
is wet-etched to remove an exposed part thereof corresponding to the emitter opening
116
.
Thereafter, in a process step shown in
FIG. 14F
, an n-type polysilicon film that is to serve as an emitter electrode is deposited over the substrate. Subsequently, using a photolithography technique and an etching technique, the polysilicon film is patterned and an emitter polysilicon electrode
113
is formed. Thereafter, thermal annealing such as RTA is performed to diffuse an n-type impurity from the emitter polysilicon electrode
113
into the Si cap layer in the Si/SiGe layer
107
such that an Si emitter layer is formed on an SiGe base layer. In this manner, an emitter and base junction is formed.
By following the process steps described above, an SiGe-HBT having an Si—SiGe heterojunction is formed.
FIG. 15
shows a schematic cross-section of an Si/SiGe layer
107
of an SiGe-HBT taken along the line XV—XV shown in FIG.
14
F and the profile of the Ge content of the Si/SiGe layer
107
in the depth direction. As shown in
FIG. 15
, the Si/SiGe layer
107
includes a non-doped SiGe spacer layer
107
a
located directly on the N
−
epitaxial layer
103
, a graded SiGe layer
107
b
provided on the SiGe spacer layer
107
a
, and an Si cap layer
107
c
. The upper portion of the Si cap layer
107
c
is doped with an n-type impurity by diffusion to serve as an emitter layer while the lower portion of the cap layer
107
c
serves as part of a base layer. In the graded SiGe layer
107
b
, the Ge content decreases gradually in the direction heading from the SiGe spacer layer
107
a
to the Si cap layer
107
c.
FIG. 16
is a timing chart showing a sequence of standard process steps of known SiGe epitaxial growth. Epitaxial growth of an SiGe film using UHV-CVD will be described herein. However, an epitaxial film can be also grown in a similar manner using LP-CVD or MBE.
As shown in
FIG. 16
, a wafer is loaded into a reaction chamber at a timing t
100
. Then, the temperature of the wafer is increased to a high temperature ranging from about 650° C. to 800° C. for a period from a timing t
101
to a timing t
102
. Then, annealing (pre-cleaning) is performed for a period from the timing t
102
to a timing t
103
(e.g., for about 2 to 20 min.). Specifically, a natural oxide film formed on the upper surface of a semiconductor substrate is reacted with silicon in the substrate so that SiO having a high vapor pressure is removed (sublimated) thereon. As a result, a clean Si surface is exposed in a region where epitaxial growth is intended to be performed. The reaction is represented by the following formula:
SiO
2
+Si→2SiO↑
Next, for a period from the timing t
103
to a timing t
104
, the wafer temperature is reduced to a growth temperature ranging from about 500° C. to 650° C., and then the wafer is held to stand for a period from the timing t
104
to a timing t
105
until the temperature distribution of the wafer surface is uniformalized. At the timing t
105
, each layer is started to be grown by introducing source gases such as disilane, monogermane and diboran into a process chamber at respective predetermined flow rates. In this case, for example, an SiGe spacer layer
107
a
is formed by supplying disilane (Si
2
H
6
) and monogerman (GeH
4
) to the upper surface of the wafer at constant flow rates, respectively, for a period from the timing t
105
to a timing t
106
. For the period from a timing t
106
to a timing t
107
, a graded SiGe layer
107
b
is grown by reducing the flow rate of monogerman gradually under the condition that the flow rates of disilane and diboran (B
2
H
6
) are kept constant and thereby grading the Ge content. Furthermore, an Si cap layer
107
c
is grown by supplying disilane to the upper surface of the wafer at a constant flow rate for a predetermined period of time from the timing t
107
.
Meanwhile, in recent years, non-selective epitaxial SiGe growth technique have been regarded as promising techniques that allow achievement of high-performance SiGe-HBTs. In the non-selective SiGe epitaxial growth techniques, as disclosed in Japanese Unexamined Patent Publication No. 5-175222 and Japanese Unexamined Patent Publication No. 6-69434, an SiGe epitaxial film is grown on an silicon layer while an SiGe polycrystalline film is grown on an insulating film, such as an oxide film and a nitride film, located around the silicon layer. When such a non-selective epitaxial growth technique is applied to the process steps shown in
FIGS. 14A through 14F
, a polycrystalline Si/SiGe film is formed between the nitride film
106
and the polysilicon film
110
and thus the polysilicon film
110
and the polycrystalline Si/SiGe fil

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