Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
2001-10-12
2002-10-01
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S706000, C257S693000, C257S784000
Reexamination Certificate
active
06459163
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and methods for fabricating the same, and more particularly, to a semiconductor device in which a chip is disposed on a substrate and electrically connected to external devices via array-arranged conductive elements, and a method for fabricating the semiconductor device.
BACKGROUND OF THE INVENTION
A BGA (ball grid arrayed) semiconductor device provides a semiconductor chip disposed therein with sufficient I/O connections in response to highly performing semiconductor devices desired for use with electronic products. However, such a conventional BGA semiconductor device has the following drawbacks.
First, the conventional BGA semiconductor device has its overall height to be the sum of heights including a portion of an encapsulant higher than the chip, the chip, a substrate mounted with the chip, and solder balls implanted on a bottom surface of the substrate. In other words, such a structure makes the BGA semiconductor device hard to be miniaturized in profile, unless the foregoing components of the BGA semiconductor device are individually reduced in dimension. This therefore restricts the application of the BGA semiconductor device for use in a low-profile product.
Second, in the BGA semiconductor device, the chip is bonded to the substrate by means of an adhesive. Due to a great difference in coefficient of thermal expansion between the chip and the substrate, during a temperature cycle in subsequent fabricating processes or practical operation, thermal stress is generated and leads to delamination occurring at a bonding interface between the chip and the substrate. This greatly affects quality and reliability of fabricated products.
Moreover, after mounting the chip on the substrate via the adhesive such as silver paste, in order to stabilize the adhesive for firmly bonding the semiconductor to the substrate, an additional curing process is often performed for the adhesive. This not only increases the fabrication cost, but makes the fabrication time not able to be further reduced.
Further, for the solder balls implanted in the BGA semiconductor device, due to dimensional inaccuracy of the solder balls, or the occurrence of warpage in the substrate resulted from the thermal stress, the solder balls implanted on the substrate can not be positioned in satisfactory coplanarity. This therefore detrimentally affects electrical connection established between the solder balls and the external devices such as a printed circuit board by using surface mounted technology (SMT).
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a semiconductor device and a method for fabricating the same, in which the semiconductor device can be significantly miniaturized in profile.
Another objective of the present invention is to provide a semiconductor device and a method for fabricating the same, in which thermal stress and delamination can be effectively prevented from occurrence, so as to improve quality and reliability of the semiconductor device.
A further objective of the present invention is to provide a semiconductor device and a method for fabricating the same, in which fabrication processes are simplified, and the fabrication cost is reduced.
A further objective of the present invention is to provide a semiconductor device and a method for fabricating the same, in which electrical connection of the semiconductor device to external devices can be improved.
In accordance with the foregoing and other objectives, the present invention proposes a semiconductor device and a method for fabricating the same. The semiconductor device of the invention comprises: a substrate formed with an opening, and disposed with a plurality of conductive traces on a side thereof, a chip having an active side and an opposing inactive side, and accommodated in the opening of the substrate, wherein the chip is dimensionally smaller in surface area than the opening; a plurality of first conductive elements for connecting the active side of the chip to the conductive traces on the substrate, so as to establish electrical connection between the chip and the substrate; a plurality of array-arranged second conductive elements disposed on the substrate, and electrically connected to the conductive traces on the substrate; and an encapsulant formed on the substrate for encapsulating the chip, the first conductive elements, the second conductive elements and the conductive traces, in a manner that the inactive side of the chip is coplanarly positioned with a side of the substrate with no conductive trace disposed thereon, and bottom sides of the second conductive elements are exposed to outside of the encapsulant and coplanarly positioned with a bottom side of the encapsulant.
The method for fabricating a semiconductor device of the invention comprises the steps of: providing a substrate formed with an opening, and disposed with a plurality of conductive traces on a side thereof; providing a chip having an active side and an opposing inactive side, and accommodating the chip in the opening of the substrate, wherein the chip is dimensionally smaller in surface area than the opening; forming a plurality of first conductive elements for connecting the active side of the chip to the conductive traces on the substrate, so as to establish electrical connection between the chip and the substrate; disposing a plurality of array-arranged second conductive elements on the substrate, wherein the second conductive elements are electrically connected to the conductive traces on the substrate; and forming an encapsulant on the substrate for encapsulating the chip, the first conductive elements, the second conductive elements and the conductive traces, in a manner that the inactive side of the chip is coplanarly positioned with a side of the substrate with no conductive trace disposed thereon, and bottom sides of the second conductive elements are exposed to outside of the encapsulant and coplanarly positioned with a bottom side of the encapsulant.
In a preferred embodiment of the invention, the encapsulant is formed to fill up the opening of the substrate, and the inactive side of the chip is exposed to the outside of the encapsulant, in a manner that a coplane is formed among the inactive side of the chip, a side of the encapsulant exposed to outside of the opening, and the side of the substrate disposed with the conductive traces thereon.
In another preferred embodiment of the invention, the encapsulant covers the side of the substrate with no conductive trace disposed thereon and the inactive side of the chip, thereby allowing the substrate and the chip to be interposed between the portion of the encapsulant formed on the side of the substrate having the conductive traces and the portion of the encapsulant formed on the side with no conductive trace. This therefore significantly reduces thermal stress acting between the substrate and the encapsulant, so as to effectively prevent warpage of the substrate from occurrence.
In a further preferred embodiment of the invention, a tape is adhered on the side of the substrate with no conductive trace for covering the opening, and for attaching the inactive side of the chip to the tape. Moreover, an additional encapsulant is formed on the side of the substrate with no conductive trace and the tape, corresponding to the foregoing encapsulant for encapsulating the chip, the first conductive elements, the second conductive elements and the conductive traces. This therefore makes the substrate interposed between the encapsulants.
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Clark Jasmine J B
Rothwell Figg Ernst & Manbeck
United Test Center Inc.
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