Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-28
2003-05-13
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S379000, C257S394000
Reexamination Certificate
active
06563178
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including n- and p-channel MOSFETs, each of which has a metal gate electrode, and also relates to a method for fabricating the device.
Recently, the process technology of semiconductor devices has been developed so much that a tremendously great number of semiconductor devices can now be integrated together on a single chip to realize a desired high-speed operation. Thanks to the marvelous development like this, MOSFETs have also been downsized year after year. However, as the gate insulating film of a MOSFET is thinned to catch up with this MOSFET downsizing trend, the drivability of the MOSFET decreases more and more noticeably. This is because the thinner the gate insulating film, the more and more depleted the known gate electrode of polysilicon.
Accordingly, to solve this problem, a metal gate process, in which the gate electrode is made of an alternative metal material that can suppress the gate depletion, has lately been researched and developed vigorously. A gate electrode made of such an alternative metal material will be herein called a “metal gate”. This metal gate can effectively contribute to reduction in signal propagation delay caused by the gate electrode, because the gate electrode has a relatively low resistivity. For that reason, the metal gate can increase the drivability of a MOSFET and can also reduce the signal propagation delay, thus enhancing the overall performance of the MOSFET. The metal gate is usually formed out of a single-layer refractory metal film of W or TiN or a multilayer structure consisting of two types of metal films. In the latter case, of the metal film is made of a metal (e.g., Al) having a low melting point but a very low resistivity, while the other metal film is made of a refractory metal like TiN.
Also, if the gate insulating film of SiO
2
for a known MOSFET is thinned, then a tunneling current likely flows through the gate insulating film, thus adversely increasing the leakage current flowing through the gate electrode.
Thus, to eliminate this problem, the effective thickness of a gate insulating film is tentatively increased by using a high dielectric constant material such as Ta
2
O
5
for the gate insulating film according to a proposed technique.
In a normal MOSFET fabrication process, however, after a gate electrode has been formed, an annealing process is usually performed at an elevated temperature to activate a dopant that has been introduced into source/drain regions. Accordingly, it is very difficult to attain sufficiently high thermal stability while using a low melting point material like Al for the gate electrode and a high dielectric constant material like Ta
2
O
5
for the gate insulating film.
In view of these problems, a method for fabricating a semiconductor device while using those thermally unstable materials for the gate electrode and gate insulating film was proposed in Japanese Laid-Open Publication No. 10-189966, for example. Hereinafter, the method disclosed in this document will be described with reference to
FIGS. 8A through 8D
.
First, as shown in
FIG. 8A
, an isolation region
11
is defined in a surface region of a p-type silicon substrate
10
. Next, a silicon dioxide film and a polysilicon film are deposited over the substrate
10
and then patterned, thereby forming a dummy gate insulating film
12
and a dummy gate electrode
13
. Thereafter, a sidewall
14
of silicon nitride is formed on the side faces of the dummy gate electrode
13
. Subsequently, using the dummy gate electrode
13
and sidewall
14
as a mask, ions of a dopant are implanted into the substrate
10
and then an annealing process is performed to activate the dopant introduced. In this manner, a doped layer
15
, which will be source/drain regions, is formed. Subsequently, an interlayer dielectric film
16
of silicon dioxide is deposited over the dummy gate electrode
13
and then planarized by a CMP process, thereby exposing the upper surface of the dummy gate electrode
13
.
Next, as shown in
FIG. 8B
, the dummy gate electrode
13
and dummy gate insulating film
12
are removed selectively to form a recessed groove
17
. Then, as shown in
FIG. 8C
, a Ta
2
O
5
film
18
and a metal film
19
of TiW or W are deposited in this order over the interlayer dielectric film
16
.
Subsequently, as shown in
FIG. 8D
, excessive parts of the Ta
2
O
5
and metal films
18
and
19
, exposed on the interlayer dielectric film
16
, are removed by a CMP process, thereby forming a gate insulating film
18
A and a gate electrode
19
A out of the Ta
2
O
5
and metal films
18
and
19
, respectively.
In this known method, ions of a dopant are implanted into the substrate
10
using the dummy gate electrode
13
and sidewall
14
as a mask, and an annealing process is performed to activate the dopant introduced. Then, after the dummy gate electrode
13
and dummy gate insulating film
12
have been removed, the gate insulating film
18
A and gate electrode
19
A are formed. That is to say, according to this method, the gate insulating film
18
A and gate electrode
19
A are not subjected to the annealing process at a high temperature. For that reason, a low melting point material like Al can be used for the gate electrode and Ta
2
O
5
can be used for the gate insulating film.
However, if a complementary MOS (CMOS) device, including two MOSFETs each having a metal gate, is fabricated by this known method, the MOSFETs can have their performance enhanced. But it is difficult to set a low threshold voltage for these MOSFETs. Hereinafter, this problem will be described in further detail.
An LSI of today is required to operate with its power dissipation further reduced. For that purpose, a drive voltage for a MOSFET needs to be further reduced. So the threshold voltage of a MOSFET should be as low as 0.2 to 0.3 V, whether the MOSFET is of n-channel type or p-channel type.
In a CMOS device including polysilicon gate electrodes, the gate electrodes of n- and p-channel MOSFETs are doped with n- and p-type dopants, respectively, so that the difference in work function between these gate electrodes, and eventually the threshold voltages of these MOSFETs, can be reduced.
However, the metal gate cannot be doped with an n- or p-type dopant. So the metal gate electrodes of n- and p-channel MOSFETs should be made of the same material. Accordingly, it is difficult to ensure high performance and low threshold voltages for these MOSFETs at a time.
For example, suppose a material for metal gate electrodes has a work function closer to the conduction band of the silicon bandgap. In that case, it is easy to implement an n-channel MOSFET as a surface-channel transistor, which usually exhibits high performance, so that the n-channel MOSFET has a threshold voltage as low as 0.2 to 0.3 V. However, to set the threshold voltage of a p-channel MOSFET to as low as 0.2 to 0.3 V, part of the channel region of the p-channel MOSFET near its surface should be subjected to a counter-doping process. Accordingly, the p-channel MOSFET should be realized as a buried-channel transistor, which is usually subject to short channel effects. As a result, it is difficult to ensure desired high performance for the p-channel MOSFET of that type.
Another possibility is that a material for metal gate electrodes has a work function closer to the valence band of the silicon bandgap. In that case, it is easy to implement a p-channel MOSFET as a surface-channel transistor, which usually exhibits high performance, so that the p-channel MOSFET has a threshold voltage as low as 0.2 to 0.3 V. However, to set the threshold voltage of an n-channel MOSFET to as low as 0.2 to 0.3 V, part of the channel region of the n-channel MOSFET near its surface should be subjected to a counter-doping process. Accordingly, the n-channel MOSFET should be realized as a buried-channel transistor, which is usually subject to short channel effects. As a result, it is difficult to ensure desired high performance for the n-channel MOSF
Moriwaki Masaru
Yamada Takayuki
Nguyen Dao H.
Nixon & Peabody LLP
Studebaker Donald R.
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