Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-06-28
2005-06-28
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S333000, C257S334000, C257S335000, C257S337000, C257S338000, C257S339000, C257S343000, C257S346000, C257S371000, C438S223000, C438S224000, C438S227000, C438S228000
Reexamination Certificate
active
06911694
ABSTRACT:
An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region21formed in P-type substrate1, and also formed therein spatially separated one another are a channel well region23and a medium concentration drain region24having an impurity concentration larger than that of drain well region21, which are simultaneously formed having a large diffusion depth through thermal processing. A source11sis formed in channel well region23, while a drain11dis formed in drain region24having an impurity concentration larger than that of drain region24. In addition, a gate electrode11gis formed over the well region, overlying the partially overlapped portions with well region23and drain region24and being separated from drain11d. Since the source11s, well region23, and drain region24are respectively self-aligned to the gate electrode11g, resultant transistor characteristics are stabilized, and the decrease in the on resistance and improved drain threshold voltages can be achieved. Also disclosed herein are bipolar transistors with LDMOS structures, which are capable of obviating the breakdown of gate dielectric layers even at high applied voltage and achieving improved stability in transistor characteristics.
REFERENCES:
patent: 4887142 (1989-12-01), Bertotti et al.
patent: 5610421 (1997-03-01), Contiero et al.
patent: 5917222 (1999-06-01), Smayling et al.
patent: 6130458 (2000-10-01), Takagi et al.
patent: 6267479 (2001-07-01), Yamada et al.
patent: RE37424 (2001-10-01), Contiero et al.
patent: 07-302903 (1995-11-01), None
patent: 10-335663 (1998-12-01), None
Kim et al. “Fabricating high-current power integrated circuit having lateral trench gate DMOS power device”, DERWENT ACC No. 2002-730211.
Fujimoto Keiji
Negoro Takaaki
Dickstein , Shapiro, Morin & Oshinsky, LLP
Eckert George
Ortiz Edgardo
LandOfFree
Semiconductor device and method for fabricating such device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for fabricating such device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for fabricating such device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3495570