Semiconductor device and method for designing the same

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Reexamination Certificate

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C365S205000

Reexamination Certificate

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08004878

ABSTRACT:
Disclosed herewith is a semiconductor device having an SRAM cell array capable of easily evaluating the performance of transistors and the systematic fluctuation of wiring capacity/resistance. In order to form an inversion circuit required to form a ring oscillator, a test cell is disposed at each of the four corners of the SRAM cell array and the ring oscillator is operated while charging/discharging the subject bit line. Concretely, the ring oscillator is formed on a memory cell array and the ring oscillator includes test cells disposed at least at the four corners of the memory cell array respectively. At this time, a wiring that is equivalent to a bit line is used to connect the test cells to each another.

REFERENCES:
patent: 7142064 (2006-11-01), Chan et al.
patent: 2006/0097802 (2006-05-01), Chan et al.
patent: 2008/0094878 (2008-04-01), Joshi et al.

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