Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2003-04-14
2008-11-04
Parekh, Nitin (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S787000, C257SE23133, C438S959000, C438S118000, C438S127000
Reexamination Certificate
active
07446423
ABSTRACT:
In a semiconductor device provided with a thinned semiconductor element, the present invention intends to inhibit damage of the semiconductor element in the neighborhood of its outer periphery so as to improve reliability. A plurality of external connection terminals are formed on a front surface of the thinned semiconductor element. A plate higher in rigidity than the semiconductor element is adhered with a resin binder to a rear surface of the semiconductor element. An outer shape of the plate is made larger than that of the semiconductor element, and the resin binder covers a side face of the semiconductor element to form a reinforcement portion for reinforcing a periphery of the semiconductor element.
REFERENCES:
patent: 4301464 (1981-11-01), Otsuki et al.
patent: 5844309 (1998-12-01), Takigawa et al.
patent: 5942048 (1999-08-01), Fujisaki et al.
patent: 6023096 (2000-02-01), Hotta et al.
patent: 6064114 (2000-05-01), Higgins, III
patent: 6175075 (2001-01-01), Shiotsuka et al.
patent: 6300576 (2001-10-01), Nakamura et al.
patent: 6617655 (2003-09-01), Estacio et al.
patent: 6656765 (2003-12-01), DiCaprio
patent: 6717279 (2004-04-01), Koike
patent: 6797544 (2004-09-01), Sakai et al.
patent: 6958544 (2005-10-01), Sunohara
patent: 2-192195 (1990-07-01), None
patent: 8-31872 (1996-02-01), None
patent: 10-135386 (1998-05-01), None
patent: 10-284634 (1998-10-01), None
patent: 11-126856 (1999-05-01), None
patent: 11-251360 (1999-09-01), None
patent: 2001-203298 (2001-07-01), None
patent: 2002-134641 (2002-05-01), None
patent: 2002-141439 (2002-05-01), None
Ozono Mitsuru
Sakai Tadahiko
Wada Yoshiyuki
Matsushita Electric - Industrial Co., Ltd.
Parekh Nitin
Wenderoth , Lind & Ponack, L.L.P.
LandOfFree
Semiconductor device and method for assembling the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for assembling the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for assembling the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4050432