Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2007-08-24
2009-02-24
Yoha, Connie C (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189011, C365S230030
Reexamination Certificate
active
07495978
ABSTRACT:
In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.
REFERENCES:
patent: 4661929 (1987-04-01), Aoki et al.
patent: 5440521 (1995-08-01), Tsunozaki et al.
patent: 5459690 (1995-10-01), Rieger et al.
patent: 5652687 (1997-07-01), Chen et al.
patent: 5808944 (1998-09-01), Yoshitake et al.
patent: 5818792 (1998-10-01), Sasaki et al.
patent: 5841708 (1998-11-01), Nagata
patent: 5970003 (1999-10-01), Miyatake et al.
patent: 6084807 (2000-07-01), Choi
patent: 6092223 (2000-07-01), Ahn
patent: 6104647 (2000-08-01), Horiguchi et al.
patent: 6233181 (2001-05-01), Hidaka
patent: 6256237 (2001-07-01), Ho et al.
patent: 6317355 (2001-11-01), Kang
patent: 6373776 (2002-04-01), Fujisawa et al.
patent: 6400596 (2002-06-01), Takemura et al.
patent: 6603688 (2003-08-01), Hasegawa et al.
patent: 6847566 (2005-01-01), Han et al.
patent: 6909646 (2005-06-01), Hasegawa et al.
patent: 58 60489 (1983-04-01), None
patent: 59178698 (1984-10-01), None
patent: 60 151895 (1985-08-01), None
patent: 60 151896 (1985-08-01), None
patent: 60 151899 (1985-08-01), None
patent: 61 20300 (1986-01-01), None
patent: 61 77946 (1994-06-01), None
patent: 7-29632 (1995-11-01), None
patent: 11 219597 (1999-10-01), None
Micropatent PatSearch—Abstract of JP 07-296328, Nov. 10, 1995.
S. Narumi et al., “Simulation of the write filed for T-shaped pole heads”, Journal of Applied Physics, vol. 87, No. 9, Parts 2 and 3, May 1, 2000.
Hasegawa Masatoshi
Kajigaya Kazuhiko
Antonelli, Terry Stout & Kraus, LLP.
Elpida Memory Inc.
Yoha Connie C
LandOfFree
Semiconductor device and memory circuit including a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and memory circuit including a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and memory circuit including a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4090711