Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-10-12
2003-03-11
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S501000, C257S506000, C257S508000, C257S621000, C257S920000
Reexamination Certificate
active
06531755
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method of a semiconductor device, and in particular, to a semiconductor device and a manufacturing method of a semiconductor device suitable for realizing higher packaging density.
DESCRIPTION OF THE RELATED ART
Miniaturization and integration of semiconductor devices are proceeding with very high speed and the width (line) of wires and the interval (space) between wires in the integrated circuits are becoming smaller and smaller. When the interval (space) between wires becomes smaller, the electric capacity between the wires increases and thereby signal speed on the wires is necessitated to be lowered. As countermeasures for resolving the problem, wires which are made of low-resistance metallic materials, low-permittivity films (low-permittivity interlayer insulating (dielectric) layers) which are placed between the wires, etc. can be used. As for the low-permittivity films, a relative dielectric constant of 2.5 or smaller can not be implemented by a high density film, therefore films or layers having microvoids can be regarded as good candidates. However, when the low-permittivity layer (film) is processed (etched) and thereby the microvoids are exposed on the processed (etched) surface of the layer, the following processes might be affected by the exposed microvoids. For example, when the processed surface of the layer has to be coated by metal in the next process, the metal coating can not be done successfully due to the existence of the microvoids on the processed surface.
In the following, an example of a conventional manufacturing method of a semiconductor device employing porous silica will be explained in detail. Incidentally, the “porous silica” means an SiO
2
layer which includes microvoids whose diameters are 10 Å~100 Å and which also includes Si—H bonds, Si—CH
3
bonds, Si—C
2
H
5
bonds, and/or Si—C
6
H
5
(phenyl group) bonds.
FIG.
1
A through
FIG. 3
are cross sectional views showing the conventional manufacturing method of a semiconductor device employing the porous silica for the interlayer insulating layer, which has been conducted by the present inventor.
First, a first P-SiN (Plasma SiN) layer
402
of a thickness of about 500 Å was formed on Cu wiring
401
by means of plasma CVD (Chemical Vapor Deposition). Subsequently, porous silica was coated on the first P-SiN layer
402
and baked at 400° C. for 30 minutes, thereby a porous silica layer
403
of a thickness of about 4000 Å was formed. On the first porous silica layer
403
, a first P-SiO
2
(Plasma SiO
2
) layer
404
of a thickness of about 500 Å was formed (FIG.
1
A). Subsequently, a first photoresist layer
405
was patterned on the first P-SiO
2
layer
404
(FIG.
1
B). Subsequently, the first P-SiO
2
layer
404
and thereafter the first porous silica layer
403
were processed (etched) using the first photoresist layer
405
as a mask. The etching was stopped at the first P-SiN layer
402
(FIG.
1
C). Subsequently, the first photoresist layer
405
was removed by means of oxygen plasma ashing and thereafter wet stripping was conducted (FIG.
2
A). Subsequently, part of the first P-SiN layer
402
corresponding to the etched part of the first porous silica layer
403
was removed by etching back (using no mask), thereby the Cu wiring
401
was exposed (FIG.
2
B).
Subsequently, RF plasma etching was conducted in a sputter chamber and thereafter a first TaN layer
406
of a thickness of about 500 Å was formed by means of collimated sputtering (FIG.
2
C). As shown in
FIG. 2C
, due to the roughness (microvoids) of the processed (etched) surface of the first porous silica layer
403
, the first TaN layer
406
could not be deposited successfully on the processed surface of the first porous silica layer
403
. Subsequently, a first Cu seed layer
407
was sputtered to a thickness of about 500 Å and thereafter a first Cu plating layer
408
was formed thereon (FIG.
3
). At the stage which is shown in
FIG. 3
, a plurality of voids
409
had occurred in the plug (via hole).
As explained above, in the conventional manufacturing method of a semiconductor device employing porous silica for the interlayer insulating layer, the processed (etched) surface of the porous silica tends to be uneven due to the microvoids, thereby the barrier metal layer (first TaN layer
406
) and the seed layer (first Cu seed layer
407
) which are formed so as to cover the processed surface of the porous silica are necessitated to have pin holes and/or thin parts. Due to the irregularity of the barrier metal layer and the seed layer, the plug (first Cu plating layer
408
) which is formed on the seed layer also tends to have voids, and thereby the resistance of the plug (via hole) becomes unstable.
SUMMARY OF THE INVENTION
It is therefore the primary object of the present invention to provide a semiconductor device and a manufacturing method of a semiconductor device by which the unevenness of the processed surface of the interlayer insulating layer can be avoided even when a low-permittivity layer made of low density materials (porous silica, for example) is used as the interlayer insulating layer, thereby the occurrence of the voids in the plug (via hole) can be eliminated, and thereby stable performance of the semiconductor device can be ensured.
In accordance with a first aspect of the present invention, there is provided a semiconductor device in which an interlayer insulating layer is formed of a low density material and a hole or a trench is formed in the interlayer insulating layer by processing the interlayer insulating layer and an electrically conductive material is coated on the processed surface of the hole or trench for establishing electrical connection. In the semiconductor device, the density of part of the interlayer insulating layer near the processed surface of the hole or trench is increased in comparison with other parts of the interlayer insulating layer.
In accordance with a second aspect of the present invention, in the first aspect, the low density material is a porous material.
In accordance with a third aspect of the present invention, in the second aspect, the porous material is porous silica.
In accordance with a fourth aspect of the present invention, in the third aspect, the porous silica at least includes Si—H bonds and/or Si—CH3 bonds.
In accordance with a fifth aspect of the present invention, there is provided a semiconductor device in which an interlayer insulating layer is formed of a low density material and a hole or a trench is formed in the interlayer insulating layer by processing the interlayer insulating layer and an electrically conductive material is coated on the processed surface of the hole or trench for establishing electrical connection. In the semiconductor device, microvoids are removed in part of the interlayer insulating layer near the processed surface of the hole or trench.
In accordance with a sixth aspect of the present invention, in the fifth aspect, the low density material is a porous material.
In accordance with a seventh aspect of the present invention, in the sixth aspect, the porous material is porous silica.
In accordance with an eighth aspect of the present invention, in the seventh aspect, the porous silica at least includes Si—H bonds and/or Si—CH3 bonds.
In accordance with a ninth aspect of the present invention, there is provided a manufacturing method of a semiconductor device having an interlayer insulating layer which is formed of a low density material. The manufacturing method comprises a processing step, a densification step and a conductive material coating step. In the processing step, the interlayer insulating layer is processed and thereby a hole or a trench is formed in the interlayer insulating layer. In the densification step, the density of part of the interlayer insulating layer near the processed surface of the hole or trench is increased. In the conductive material coating step, an ele
Flynn Nathan J.
Forde Remmon R.
NEC Corporation
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