Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-08-16
2011-08-16
Fahmy, Wael M (Department: 2895)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257SE21382, C257SE29197, C257S409000, C257S493000, C438S135000, C438S138000, C438S435000, C438S286000
Reexamination Certificate
active
07999317
ABSTRACT:
A p-type body region and an n-type buffer region are formed on an n−drift region. An n++emitter region and a p++contact region are formed on the p-type body region in contact with each other. A p++collector region is formed on the n-type buffer region. An insulating film is formed on the n−drift region, and a gate insulating film is formed on the n++emitter region, the p-type body region, and the n drift region. A gate electrode is formed on the insulating film and the gate insulating film. A p+low-resistivity region is formed in the p-type body region and surrounding the interface between the n++emitter region and between the p-type body region and the p++contact region. The p-type body region has two local maxima of an impurity concentration profile at the interface between the body region and the gate insulating film.
REFERENCES:
patent: 5079602 (1992-01-01), Harada et al.
patent: 5304827 (1994-04-01), Malhi et al.
patent: 5326993 (1994-07-01), Iwamuro
patent: 5349225 (1994-09-01), Redwine et al.
patent: 5397905 (1995-03-01), Otsuki et al.
patent: 5514608 (1996-05-01), Williams et al.
patent: 5644150 (1997-07-01), Iwamuro
patent: 5665988 (1997-09-01), Huang
patent: 5970343 (1999-10-01), Kocon
patent: 6064086 (2000-05-01), Nakagawa et al.
patent: 6117738 (2000-09-01), Tung
patent: 6130458 (2000-10-01), Takagi et al.
patent: 6222233 (2001-04-01), D'Anna
patent: 6242787 (2001-06-01), Nakayama et al.
patent: 6424005 (2002-07-01), Tsai et al.
patent: 6528848 (2003-03-01), Hoshino et al.
patent: 6677622 (2004-01-01), Suzuki et al.
patent: 6974753 (2005-12-01), Beasom
patent: 7238987 (2007-07-01), Ikuta et al.
patent: 7265416 (2007-09-01), Choi et al.
patent: 7268045 (2007-09-01), Hower et al.
patent: 7531888 (2009-05-01), Cai
patent: 7602025 (2009-10-01), Nishimura et al.
patent: 7605040 (2009-10-01), Choi et al.
patent: 7671411 (2010-03-01), You et al.
patent: 7719086 (2010-05-01), Ikuta et al.
patent: 7786532 (2010-08-01), Terashima
patent: 2001/0012671 (2001-08-01), Hoshino et al.
patent: 2002/0005559 (2002-01-01), Suzuki
patent: 2002/0017697 (2002-02-01), Kitamura et al.
patent: 2002/0030224 (2002-03-01), Hshieh et al.
patent: 2002/0048855 (2002-04-01), Matsudai et al.
patent: 2002/0125542 (2002-09-01), Suzuki et al.
patent: 2003/0107050 (2003-06-01), Letavic et al.
patent: 2003/0141559 (2003-07-01), Moscatelli et al.
patent: 2005/0067653 (2005-03-01), Litwin et al.
patent: 2005/0085023 (2005-04-01), Letavic et al.
patent: 2005/0205897 (2005-09-01), Depetro et al.
patent: 2006/0113592 (2006-06-01), Pendharkar et al.
patent: 2006/0118902 (2006-06-01), Ikuta et al.
patent: 2007/0120201 (2007-05-01), Yamaguchi et al.
patent: 2008/0012043 (2008-01-01), Udrea et al.
patent: 2008/0135972 (2008-06-01), Ikuta et al.
patent: 2008/0179663 (2008-07-01), Terashima
patent: 2009/0057712 (2009-03-01), Terashima
patent: 01-125979 (1989-05-01), None
patent: 06-244430 (1994-09-01), None
patent: 2001-094094 (2001-04-01), None
patent: 2002-270844 (2002-09-01), None
patent: 2005-109226 (2005-04-01), None
patent: 2006-165145 (2006-06-01), None
Disney et al., “SOI LIGBT Devices with a Dual P-Well Implant for Improved Latching Characteristics,” 5th International Symposium on Power Semiconductor Devices and ICs, pp. 254-258, IEEE.
Mok et al., “A Self-Aligned Trenched Cathode Lateral Insulated Gate Bipolar Transistor with High Latch-up Resistance,” IEEE Transactions on Electron Devices, 1995, vol. 42, No. 12, p. 2236-2239, IEEE.
Lu Hong-Fei
Tomonori Mizushima
Fahmy Wael M
Fuji Electric Systems Co., Ltd.
Rabin & Berdo P.C.
Singal Ankush k
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