Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-09-21
2001-04-10
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C258S005000, C258S005000, C438S210000
Reexamination Certificate
active
06215187
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having a capacitor and a contact plug in an MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a DRAM (Dynamic Random Access Memory) or the like, and to a manufacturing method thereof.
2. Description of the Background Art
As the technique of manufacturing semiconductors and especially the technique of miniature processing have been developed, degree of integration and capacity of DRAMs for MOS transistors have been increased. As the degree of integration increases, the area occupied by a semiconductor element per 1 bit has been decreased. Therefore, the area of a capacitor storing information (charges) decreases, and hence charges stored therein decreases. As a result, the capacitor has come to be very sensitive to slight electrical influence, so that there have been problems of erroneous calling of information where charges are erroneously injected to the capacitor or charges are erroneously ejected from the capacitor, as well as the problem of soft error in which the contents of the memory is destroyed by &agr; ray or the like. Further, as the semiconductor device has been reduced in size, contact area between a transistor and an interconnection or a contact area of a contact plug connecting interconnections with each other is reduced, so that contact resistance at the content portion is increased. This means that excessive voltage is required in a highly miniaturized semiconductor devices and that power consumption increases.
In order to address one of the aforementioned problems, that is, reduction of capacitor capacitance resulting from miniaturization of the semiconductor devices, various methods have been proposed to increase area of occupation in a capacitor using a polycrystalline silicon film or the like for the storage electrode. According to one of the proposed methods, the storage electrode is formed in a cylindrical shape, so as to increase contact area in a direction vertical to the main surface of the semiconductor substrate.
The structure of a conventional cylindrical capacitor and manufacturing method thereof will be described with reference to
FIGS. 22
to
28
. First, on a P type silicon substrate
102
, an isolating oxide film
105
a
is formed, resulting in separate element forming regions. On the element forming region formed separately by isolating oxide film
105
a
, a gate oxide film
104
c
and a gate electrode
104
(word line) of a two-layered structure including a high melting point metal silicide film
104
a
and a polycrystalline silicon film
104
b
are formed. Thereafter, using gate electrode
104
as a mask, source/drain regions
103
, which are n
−
diffusion layers, are formed by impurity implantation. In this manner, an MOSFET, that is, an MOS field effect transistor is formed. Thereafter, to cover gate electrode
104
and isolating oxide film
105
a
, an interlayer oxide film
105
b
is deposited on semiconductor substrate
102
. Thereafter, a contact hole
106
a
is formed to be connected to source/drain region
103
. Thereafter, a contact plug is filled in contact hole
106
a
, and etched to a prescribed shape. Thus, a bit line
106
connected to the MOS field effect transistor is formed as shown in FIG.
22
. Then, an interlayer oxide film
105
c
is deposited on interlayer oxide film
105
b
, and a contact hole
107
a
for forming a plug establishing electrical connection between source/drain region
103
and a storage electrode of the capacitor is formed. Thereafter, a conductive material is filled in contact hole
107
a
, so that a contact plug
107
is formed. Thereafter, an interlayer oxide film
105
j
is deposited on interlayer oxide film
105
c
and contact plug
107
. On interlayer oxide film
105
j
, a prescribed mask is formed, and thereafter, a contact hole
150
in which a capacitor is to be formed, is formed by etching as shown in FIG.
24
. Thereafter, a polycrystalline silicon film, which is to be storage electrodes
108
a
and
108
b
, is formed in contact hole
150
. Thereafter, a capacitor dielectric film
101
is formed to cover an upper surface of interlayer oxide film
105
j
and surfaces of storage electrodes
108
a
and
108
b
. Thereafter, a film which is to be a cell plate electrode
109
, is deposited to cover capacitor dielectric film
101
, and in this manner, the capacitor is completed.
As the two-dimensional area of semiconductor substrate
102
occupied by the semiconductor device decreases, the capacitor formed through the above described steps has come to be formed extending considerably large in the vertical direction with respect to semiconductor substrate
102
. In other words, contact hole
105
in which the capacitor is formed is large in the vertical direction with respect to the main surface of semiconductor substrate
102
.
Therefore, generally, contact hole
150
in which storage electrode
109
is formed has an upper portion of interlayer oxide film
105
j
etched by larger amount than the lower portion through dry etching as can be seen from
FIG. 25
, and therefore the contact hole come to have an inverted frusto-conical shape with inclined sidewalls, of which opening diameter gradually increases from the lower portion to the upper portion of interlayer oxide film
105
j
. Therefore, when a two-dimensionally small contact hole
150
is to be formed, the lower portion of contact hole
150
come to have too small an opening diameter relative to the upper portion. As a result, at the lower portion of contact hole
150
, the conductive material for forming the film to be the storage electrode
109
may not be sufficiently filled but clogged.
If the conductive material for forming the film to be cell plate electrode
109
is not properly filled in the lower portion of contact hole
150
, surface area of that portion which functions as an electrode of cell plate electrode
109
reduces, resulting in reduced electrostatic capacitance of the capacitor. Even when the conductive material for forming the film to be cell plate electrode
109
is properly filled, cell plate electrode
109
becomes very thin at the lower portion of contact hole
105
, and therefore it becomes difficult to store sufficient charges. Thus the function of the cell plate electrode cannot be ensured.
Further, the higher the height of the capacitor from the main surface of semiconductor substrate
102
, contact hole
150
come to have the higher aspect ratio.
Here, as the sidewalls of contact hole
150
are inclined, the opening diameter is small at the lower portion of contact hole
150
, and further, a phenomenon referred to as bowing, where the opening diameter at the upper portion of contact hole
150
come to be smaller than the middle portion of contact hole
150
, is observed. When the phenomenon of bowing occurs in contact hole
150
, a material
170
formed along contact hole
150
provided in interlayer oxide film
105
k
cannot be properly filled, resulting in undesirable void inside the material
170
.
Further, problems experienced in contact plug
107
will be described with reference to
FIGS. 27 and 28
.
FIG. 27
is a cross section taken along the line B—B of FIG.
23
. As can be seen from
FIG. 27
, contact plug
107
is required of a small opening diameter at an upper portion of contact hole
107
a
, considering short-circuit with bit line
106
. Therefore, when the contact hole is formed in the frusto-conical shape in a two dimensionally small semiconductor device as described above, the opening diameter at the lower portion becomes considerably small. Accordingly, the contact resistance at the contact between the lower surface of conductive contact plug filled in contact hole
107
a
and source/drain region
103
is high. Further, as can be seen from
FIG. 28
, when the opening diameter of contact hole
107
a
is enlarged by wet etching to reduce contact resistance to provide
Kobayashi Heiji
Nakazawa Shouitirou
Ooto Kenichi
Jr. Carl Whitehead
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Potter Roy
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