Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2004-12-07
2008-11-25
Le, Thao P. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000
Reexamination Certificate
active
07456472
ABSTRACT:
A semiconductor device comprising a multi Fin-FET structure capable of suppressing short channel effects, controlling a threshold voltage, driving a high current, and operating in a high-speed comprises a source region and a drain region disposed on a semiconductor substrate, a plurality of fins interconnecting the source region and drain region, a first gate electrode disposed on the semiconductor substrate and to one side face of each fin, a second gate electrode disposed on the semiconductor substrate and to the other side face of the fin to face the first gate electrode, and separated from the first gate electrode, a plurality of first pad electrodes connected to respective first gate electrode, a first wiring interconnecting the plurality of first pad electrodes, a plurality of second pad electrodes connected to respective second gate electrode, and a second wiring interconnecting the plurality of second pad electrodes.
REFERENCES:
patent: 5910677 (1999-06-01), Irino
patent: 6507124 (2003-01-01), Kumagai et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6803631 (2004-10-01), Dakshina-Murthy et al.
patent: 6872647 (2005-03-01), Yu et al.
patent: 6888187 (2005-05-01), Brown et al.
patent: 6897527 (2005-05-01), Dakshina-Murthy et al.
patent: 7300837 (2007-11-01), Chen et al.
patent: 2002/0036290 (2002-03-01), Inaba et al.
patent: 2002/0053739 (2002-05-01), Honma et al.
patent: 2003/0006795 (2003-01-01), Asayama et al.
patent: 2005/0051843 (2005-03-01), Inaba
patent: 2005/0077550 (2005-04-01), Inaba et al.
patent: 2007/0287256 (2007-12-01), Chang et al.
patent: 2007/0290250 (2007-12-01), Clark et al.
patent: 2007/0292996 (2007-12-01), Abadeer et al.
patent: 2008/0099795 (2008-05-01), Bernstein et al.
patent: 2008/0153213 (2008-06-01), Fazan
patent: 1186342 (1998-07-01), None
patent: 2001-298194 (2001-10-01), None
patent: 2001-358232 (2001-12-01), None
patent: 2002-110963 (2002-04-01), None
patent: 2002-141482 (2002-05-01), None
patent: 2003-298051 (2003-10-01), None
D. Hisamoto et al., “A Folded-channel MOSFET for Deep-sub-tenth Micron Era,” IEDM Technology Digest, (1998), pp. 1032-1034.
X. Y. Liu et al., “Flexible Threshold Voltage FinFETs with Independent Double Gates and an Ideal Rectangular Cross-Section Si-Fin Channel,” IEDM Technology Digest, (2003), pp. 986-988.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” IEDM Technology Digest, (2001), pp. 421-424.
U.S. Appl. No. 11/097,387, filed Apr. 4, 2005, Inaba.
U.S. Appl. No. 11/100,559, filed Apr. 7, 2005, Inaba.
Foley & Lardner LLP
Kabushiki Kaisha Toshiba
Le Thao P.
LandOfFree
Semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4049045