Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2006-05-18
2008-11-25
Norton, Nadine (Department: 1792)
Semiconductor device manufacturing: process
Chemical etching
C438S149000, C257S059000, C257S072000, C257S151000
Reexamination Certificate
active
07456104
ABSTRACT:
To provide a thin film integrated circuit at low cost and with thin thickness, which is applicable to mass production unlike the conventional glass substrate or the single crystalline silicon substrate, and a structure and a process of a thin film integrated circuit device or an IC chip having the thin film integrated circuit. A manufacturing method of a semiconductor device includes the steps of forming a first insulating film over one surface of a silicon substrate, forming a layer having at least two thin film integrated circuits over the first insulating film, forming a resin layer so as to cover the layer having the thin film integrated circuit, forming a film so as to cover the resin layer, grinding a backside of one surface of the silicon substrate which is formed with the layer having the thin film integrated circuit, and polishing the ground surface of the silicon substrate.
REFERENCES:
patent: 5155068 (1992-10-01), Tada
patent: 5382537 (1995-01-01), Noguchi
patent: 6682963 (2004-01-01), Ishikawa
patent: 7105423 (2006-09-01), Yamano et al.
patent: 2002/0030189 (2002-03-01), Ishikawa
patent: 2004/0164302 (2004-08-01), Arai et al.
patent: 2005/0023525 (2005-02-01), Ishikawa
patent: 2005/0282306 (2005-12-01), Yamanaka
patent: 1 453 088 (2004-09-01), None
patent: 03-087299 (1991-04-01), None
patent: 11-020360 (1999-01-01), None
patent: 11-212116 (1999-08-01), None
patent: 2002-164354 (2002-06-01), None
patent: 2004-094492 (2004-03-01), None
patent: 2004-282050 (2004-10-01), None
D.N. Kouvatsos, Electronics Letters, vol. 32, No. 8, pp. 775-776.
M Reeiche, Advanced Packing , Mrch (2003) pp. 1-8.
Usami et al., “17.1 An SOI-Based 7.5 μm-Thick 0.15×0.15mm2RFID Chip,” ISSCC 2006 (Digest of Technical Papers, IEEE International Solid-State Circuits Conference), pp. 308-309 and 655.
Kusumoto Naoto
Tsurume Takuya
Angadi Maki
Norton Nadine
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4027125