Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2006-09-26

2006-09-26

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S350000, C257SE31086

Reexamination Certificate

active

07112833

ABSTRACT:
The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012cm−2or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012cm−2or more.

REFERENCES:
patent: 6207506 (2001-03-01), Yi et al.
patent: 6459126 (2002-10-01), Mogami et al.
patent: 6885105 (2005-04-01), Kakamu et al.
patent: 2002/0185693 (2002-12-01), Yasuda et al.
patent: 11-135774 (1999-05-01), None
E. Gusev et al, “Ultrathin High-K Gate Stacks for Advanced CMOS Devices”, IEEE, IEDM 2001 Tech. Digest, 2001, 4 pp.
Z. Luo et al, “Ultra-thin ZrO2 (or Silicate) with High Thermal Stability for CMOS Gate Applications”, 2001 Symposium on VLSI Technology Digest of Technical Papers, 2001, 2 pp.
D. Buchanan et al, “80 nm Poly-silicon Gated n-FETs with Ultra-thin AI2O3 Gate Dielectric for ULSI Applications”, IEDM 200 Tech. Digest, 2000, 4 pp.
M. Hiratani et al, “Effective Electron Mobility Reduced by Remote Charge Scattering in High-k Gate Stacks”, Jpn. J. Appl. Phys., vol. 41, 2002, pp. 4521-4522.

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