Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1994-06-02
1995-04-11
Wojciechowicz, Edward
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257298, 257306, 257347, 257350, 437 48, 437 49, 437 52, 437 59, 437 84, 437190, 437915, H01L 2978, H01L 21265
Patent
active
054061024
ABSTRACT:
A surface stepped portion of the top interlayer insulating layer is reduced. An insulating layer is formed on the entire surface of a silicon substrate. A silicon layer is formed on and in contact with an upper surface of insulating layer. A pair of source/drain regions are formed in silicon layer with a predetermined space. A gate electrode is formed on a region sandwiched by the pair of source/drain regions with a gate insulating layer interposed therebetween. A bit line is formed in connection with source/drain region, and extending in contact with an upper surface of insulating layer. A capacitor configured of a lower electrode layer, a capacitor insulating layer, and an upper electrode layer is formed in contact with source/drain region through a contact hole formed in an interlayer insulating layer.
REFERENCES:
patent: 5347151 (1994-09-01), Shimizu et al.
Novel SOI CMOS Design using Ultra Thin Near Intrinsic Substrate S. D. S. Malhi et al. IEDM 82, pp. 107-110 Dec. 1982.
A Buried Capacitor DRAM Cell with Bonded SOI for 256M and 1GBIT DRAMS, Toshiyuki Nishihara et al., IEDM 92, pp. 803-806 Dec. 1992.
Mitsubishi Denki & Kabushiki Kaisha
Wojciechowicz Edward
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