Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-22
2004-08-31
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S235000, C257S245000, C257S249000, C257S382000, C257S412000
Reexamination Certificate
active
06784471
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method.
2. Description of the Background Art
Conventional semiconductor devices, instead of being restricted to MOS field effect transistors (MOSFETs), are generally formed on a silicon substrate. Particularly, power semiconductor devices usually have such a structure that an epitaxial layer is disposed on a single crystal silicon substrate and a semiconductor layer is disposed in the surface of the epitaxial layer. This is because the use of the epitaxial layer facilitates controls of specific resistance value and crystal defect.
As example of conventional MOSFETs, the configuration of a trench gate type MOSFET
90
is shown in FIG.
20
.
Referring to
FIG. 20
, the MOSFET
90
has an epitaxial layer
102
formed by epitaxial growth on a main surface of a silicon substrate
101
containing an n-type impurity at a relatively high concentration (n
+
). The epitaxial layer
102
contains an n-type impurity at a relatively low concentration (n
+
). A channel dope layer
103
containing a p-type impurity is disposed in the entire surface of the epitaxial layer
102
.
A plurality of trenches
104
are disposed which extend from the main surface of the channel dope layer
103
and pass through the layer
103
to the inner part of the epitaxial layer
102
. A gate oxide film
105
is disposed so as to cover the inner walls of the trenches
104
and the main surface of the channel dope layer
103
surrounding the trenches
104
. Regions of the trenches
104
that are surrounded by the gate oxide film
105
are filled with a doped polysilicon containing a semiconductor impurity, thereby forming a gate electrode
106
.
The peripheral portions of the upper surface of the gate
106
is covered with an insulating film
107
. The upper part of the insulating film
107
and the upper part of the gate oxide film
105
surrounding the trenches
104
are covered with a conductor layer
108
such as of titanium. A titanium nitride (TiN) film
109
is disposed so as to cover the surface of the conductor layer
108
.
In the surface of the channel dope layer
103
, a source region
110
containing an n-type impurity in a relatively high concentration (n+) is selectively disposed so as to make contact with the both side surfaces of the trenches
104
. A contact layer
111
containing a p-type inpurity in a relatively high concentration (p
+
) provides a connection between the source regions
110
of the adjacent trenches
104
.
The surface of the contact layer
111
is covered with a titanium silicide (TiSi) film
112
, to which a source electrode
113
is connected. The source electrode
113
extends over the entire surface including the surface of the titanium nitride film
109
. In a portion not shown, the titanium nitride film
109
is exposed from the source electrode
113
and it passes through the titanium nitride film
109
, conductor layer
108
and insulating film
107
, thereby making an electrical contact with the gate electrode
106
.
A drain electrode
114
is disposed on the other main surface of the silicon substrate
101
. Through a channel formed along the side surfaces of the trenches
104
, the main current of the MOSFET
90
flows perpendicularly to a main surface of the silicon substrate
1
.
As discussed above, the epitaxial layer
102
is arranged on the silicon substrate
101
in the conventional MOSFET
90
. This arrangement increases material cost and fails to reduce manufacturing cost.
Further, the impurity concentration of the silicon substrate
101
should be increased to reduce the on-state resistance of the MOSFET
90
, but it is difficult to increase the impurity concentration while maintaining crystalline, about 1×10
20
to 1×10
21
/cm
3
would be the limit.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of reducing manufacturing cost and on-state resistance.
A semiconductor device according to a first aspect of the invention includes a metal substrate, plural active regions selectively disposed on a main surface of the metal substrate, and a conductor layer being disposed above the main surface of the metal substrate and making electrical connection with the plural active regions, the plural active regions being electrically independent from one another in a direction horizontal to the main surface of the metal substrate and using the conductor layer and the metal substrate as a main electrode, so that a main current flows in a direction perpendicular to the main surface of the metal substrate in each of the plural active regions.
The plural active regions, each of which is electrically independent in a direction horizontal to the main surface of the metal substrate, are disposed on the main surface of the metal substrate, so that the main current flows in a direction perpendicular to the main surface of the metal substrate in the active regions. Thereby, the substrate cost and manufacturing cost can be reduced than may be the case of using a silicon substrate. Further, the use of the metal substrate reduces the substrate resistance and on-state resistance.
A method of manufacturing a semiconductor device according to a second aspect of the invention includes the following steps (a) to (j). The step (a) is to prepare a metal substrate. The step (b) is to form a first insulating film having a predetermined pattern on a main surface of the metal substrate. The step (c) is to bury a region defined by the pattern of the first insulating film with an impurity layer containing impurity of a first conductivity type. The step (d) is to form a full-face polysilicon layer over the entire upper parts of the first insulating film and the impurity layer. The step (e) is to subject the full-face polysilicon layer to ion implantation of impurity of a second conductivity type, followed by heat treatment, so that the impurity of the second conductivity type is diffused into the full-face polysilicon layer and the impurity of the first conductivity type in the impurity layer is diffused into the full-face polysilicon layer, thereby forming plural first semiconductor layers in the surface of a first main surface on the side of the metal substrate in the full-face polysilicon layer. The step (f) is to remove part of the full-face polysilicon layer which corresponds to the upper part of the first insulating film, to form plural polysilicon layers, each having one of the plural first semiconductor layers. The step (g) is to form a second insulating film so as to cover each of the plural polysilicon layers. The step (h) is to bury a trench gate in a trench region surrounded and defined by the first and second insulating films. The step (i) is, in the state that the trench gate is buried, to subject the plural polysilicon layers to ion implantation of impurity of a second conductivity type, to form a second semiconductor layer in the surface of a second main surface of the opposite side of the first main surface in each of the plural polysilicon layers. And the step (j) is to form above the main surface of the metal substrate a conductor layer electrically connected to the second semiconductor layer.
It is capable of disposing on the main surface of the metal substrate the MOSFET in which the main current flows in a direction perpendicular to the main surface of the metal substrate. In addition, the first semiconductor layer can be formed in the surface of the first main surface of the full-face polysilicon layer by diffusing the impurity layer of the first conductivity type that is buried in the region defined by the pattern of the first insulating film. This makes it easy to form the first semiconductor layer to be located at the lowermost layer.
A method of manufacturing a semiconductor device according to a third aspect of the invention includes the following steps (a) to (j). The step (a) is to prepare a metal substrate having on its main surface an impurity lay
Louie Wai-Sing
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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