Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2002-03-19

2004-05-25

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S197000

Reexamination Certificate

active

06740939

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to CMOS transistors and a manufacturing method thereof.
2. Description of the Background Art
In formation of CMOS (Complementary MOS) transistors which use N-channel MOSFETs (referred to as NMOS transistors hereinafter) and P-channel MOSFETs (referred to as PMOS transistors hereinafter) in combination, it is required that the gate electrodes of the NMOS and PMOS transistors suit their respective characteristics.
In MOS transistors having gate lengths up to 0.25 to 0.35 &mgr;m, surface-channel type transistors are used as the NMOS transistors and buried-channel type transistors are used as the PMOS transistors, both of which use polysilicon which is doped with impurity, phosphorus (P), as the gate electrodes.
However, the PMOS transistors, adopting the buried-channel structure, are difficult to downsize, since the channel is formed inside the substrate; recent devices therefore adopt the surface-channel structure in both of the NMOS and PMOS transistors, where dual-gate process is becoming common in which N-type impurities are introduced into the gate electrodes of the NMOS transistors and P-type impurities are introduced into the gate electrodes of the PMOS transistors. In contrast to the dual-gate process, a process in which the same type of impurities are introduced into the gate electrodes of both is called a single-gate process.
In the dual-gate process, a layer of non-doped polysilicon is formed as the gate electrodes and impurities are introduced during the gate implantation process and source/drain implantation process.
However, in surface-channel type devices in which the channel is formed right under the gate insulating film, a strong vertical electric field may reduce the carrier mobility. The strong electric field also considerably reduces the reliability under hot-carrier stress and the reliability under bias-temperature stress (NBTI: Negative Bias Temperature Instability).
Accordingly, in recent semiconductor devices having plural kinds of transistors with different operating voltages, e.g. transistors in low-voltage portion which operate at relatively low voltage and transistors in high-voltage portion which operate at relatively high voltage, the performance and reliability of the high-voltage transistors are often sacrificed.
First Conventional Example
First, referring to
FIGS. 30
to
38
, a method for manufacturing a semiconductor device having a CMOS transistor
70
A and a CMOS transistor
70
B is described as an example of the single-gate process. The structure of the CMOS transistor
70
A designed for low voltage and that of the CMOS transistor
70
B designed for high voltage are shown in
FIG. 38
which illustrates the final process step.
First, as shown in
FIG. 30
, element isolation insulating film
20
is selectively formed in the surface of the silicon substrate
10
to define a low-voltage NMOS region LNR and a low-voltage PMOS region LPR for formation of a low-voltage NMOS transistor and a low-voltage PMOS transistor, and a high-voltage NMOS region HNR and a high-voltage PMOS region HPR for formation of a high-voltage NMOS transistor and a high-voltage PMOS transistor.
Then P well regions PW containing a P-type impurity are formed in the surface of the silicon substrate
10
in the low-voltage NMOS region LNR and the high-voltage NMOS region HNR, and N well regions NW containing an N-type impurity are formed in the surface of the silicon substrate
10
in the low-voltage PMOS region LPR and the high-voltage PMOS region HPR. In the description below, the P well regions PW and the N well regions NW may be simply called a silicon substrate together.
A gate insulating film
41
, e.g. an insulating film of silicon oxide, is then formed all over the low-voltage NMOS region LNR and the low-voltage PMOS region LPR on the silicon substrate
10
. A gate insulating film
42
, e.g. an insulating film of silicon oxide, is formed all over the high-voltage NMOS region HNR and the high-voltage PMOS region HPR on the silicon substrate
10
.
The gate insulating film
41
is formed to a thickness of about 0.5 to 3 nm in terms of silicon oxide film thickness, and the gate insulating film
42
is formed to a thickness of about 3 to 10 nm in terms of silicon oxide film thickness.
Then low-concentration impurity layers
30
are formed by introducing a P-type impurity by ion implantation to a relatively low concentration (P
−
) into the surface of the silicon substrate
10
in the low-voltage PMOS region LPR and the high-voltage PMOS region HPR.
FIG. 30
shows the process in which a P-type impurity is ion-implanted into the high-voltage PMOS region HPR, with the part except the high-voltage PMOS region HPR covered by a resist mask R
1
patterned by photolithography. P-type impurity is similarly introduced into the surface of the silicon substrate
10
in the low-voltage PMOS region LPR to form the low-concentration impurity layer
30
.
Next, in the process shown in
FIG. 31
, a non-single-crystal silicon film
50
is applied all over the surface of the silicon substrate
10
. This non-single-crystal silicon film
50
is formed of polysilicon or amorphous silicon and contains an N-type impurity, e.g. P (phosphorus).
Next, in the process shown in
FIG. 32
, the non-single-crystal silicon film
50
is patterned by photolithography to form gate electrodes
51
in the low-voltage NMOS region LNR and the low-voltage PMOS region LPR, and gate electrodes
52
in the high-voltage NMOS region HNR and the high-voltage PMOS region HPR.
Next, in the process shown in
FIG. 33
, a P-type impurity is introduced by ion implantation to a relatively low concentration (P
−
) into the surface of the silicon substrate
10
in the low-voltage PMOS region LPR, so as to form a pair of extension layers
62
.
FIG. 33
shows the process in which a P-type impurity is ion-implanted into the low-voltage PMOS region LPR by using the gate electrode
51
as an implant mask, with the part other than the low-voltage PMOS region LPR covered by a resist mask R
2
patterned by photolithography.
The pair of extension layers
62
are provided in such a manner that they face each other through the low-concentration impurity layer
30
underneath the gate electrode
51
. In this case, the region of the silicon substrate
10
located underneath the low-concentration impurity layer
30
serves as the channel region.
The extension layers are impurity layers which form a shallower junction than main source/drain layers formed later; while they should be called source/drain extension layers since they have the same conductivity type as the main source/drain layers and function as source/drain layers, they are called extension layers for convenience. Extension layers are formed also in other regions by similar process.
FIG. 34
shows the structure obtained after the formation of extension layers in the individual regions, where pairs of extension layers
61
and
63
are formed in the surface of the silicon substrate
10
respectively in the low-voltage NMOS region LNR and the high-voltage NMOS region HNR by introducing an N-type impurity to a relatively low concentration (N
−
), and pairs of extension layers
62
and
64
are formed in the surface of the silicon substrate
10
respectively in the low-voltage PMOS region LPR and the high-voltage PMOS region HPR by introducing a P-type impurity to a relatively low concentration (P
−
).
The pair of extension layers
64
are formed in such a manner that the low-concentration impurity layer
30
is interposed between them.
FIG. 34
shows a process for forming side wall protection film (side wall insulating film) to protect the side walls of the gate electrodes
51
and
52
, where an insulating film OX
1
, e.g. a silicon oxide film, is formed all over the silicon substrate
10
.
Subsequently, in the process shown in
FIG. 35
, the parts of the insulating film OX
1
located on top of the

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